Lines Matching full:24
137 #define CAP_DP_A_SHIFT 24
138 #define CAP_DP_A_DEFAULT_MASK (1 << 24)
139 #define CAP_DP_A_FALSE (0 << 24)
140 #define CAP_DP_A_TRUE (1 << 24)
142 #define CAP_DP_B_DEFAULT_MASK (1 << 24)
143 #define CAP_DP_B_FALSE (0 << 24)
144 #define CAP_DP_B_TRUE (1 << 24)
155 #define PWR_HALT_DELAY_SHIFT 24
156 #define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24)
157 #define PWR_HALT_DELAY_DONE (0 << 24)
158 #define PWR_HALT_DELAY_ACTIVE (1 << 24)
176 #define TEST_TESTMUX_SHIFT 24
177 #define TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
178 #define TEST_TESTMUX_AVSS (0 << 24)
179 #define TEST_TESTMUX_CLOCKIN (2 << 24)
180 #define TEST_TESTMUX_PLL_VOL (4 << 24)
181 #define TEST_TESTMUX_SLOWCLKINT (8 << 24)
182 #define TEST_TESTMUX_AVDD (16 << 24)
183 #define TEST_TESTMUX_VDDREG (32 << 24)
184 #define TEST_TESTMUX_REGREF_VDDREG (64 << 24)
185 #define TEST_TESTMUX_REGREF_AVDD (128 << 24)
223 #define PLL0_ICHPMP_SHFIT 24
224 #define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
276 #define PLL2_AUX8_SHIFT 24
277 #define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
278 #define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
279 #define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
291 #define CSTM_ROTCLK_SHIFT 24
292 #define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
306 #define LVDS_ROTCLK_SHIFT 24
307 #define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
308 #define LVDS_ROTCLK_RST (0 << 24)
471 #define SEQ_INST_TRISTATE_IOS_SHIFT 24
472 #define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
473 #define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
547 #define DC_LANE3_DP_LANE3_SHIFT 24
548 #define DC_LANE3_DP_LANE3_MASK (0xff << 24)
549 #define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
550 #define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
551 #define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
552 #define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
553 #define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
554 #define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
555 #define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
556 #define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
557 #define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
558 #define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
597 #define PR_LANE3_DP_LANE3_SHIFT 24
598 #define PR_LANE3_DP_LANE3_MASK (0xff << 24)
599 #define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
600 #define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
601 #define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
602 #define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
603 #define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
604 #define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
605 #define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
606 #define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
607 #define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
608 #define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
657 #define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24
658 #define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
659 #define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
672 #define DP_MN_M_DELTA_SHIFT 24
673 #define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
679 #define DP_PADCTL_VCO_2X_SHIFT 24
680 #define DP_PADCTL_VCO_2X_DISABLE (0 << 24)
681 #define DP_PADCTL_VCO_2X_ENABLE (1 << 24)
753 #define DP_TPG_LANE3_PATTERN_SHIFT 24
754 #define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
755 #define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
756 #define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
757 #define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
758 #define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
759 #define DP_TPG_LANE3_PATTERN_D102 (4 << 24)
760 #define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
761 #define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
762 #define DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
763 #define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)