679 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)  in tegra_dc_sor_enable_dc()  argument
681 	u32 reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
683 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
684 	writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);  in tegra_dc_sor_enable_dc()
688 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_enable_dc()
689 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
762 	struct dc_ctlr *disp_ctrl;  in tegra_dc_sor_attach()  local
767 	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);  in tegra_dc_sor_attach()
769 	tegra_dc_sor_enable_dc(disp_ctrl);  in tegra_dc_sor_attach()
772 	writel(0x9f00, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
773 	writel(0x9f, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
777 	       &disp_ctrl->cmd.disp_pow_ctrl);  in tegra_dc_sor_attach()
790 	writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
791 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
792 	writel(0, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
793 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
806 	reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
807 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
809 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_attach()
810 	writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
811 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
962 static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)  in tegra_dc_sor_enable_sor()  argument
964 	u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()
967 	writel(reg_val, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()
974 	struct dc_ctlr *disp_ctrl;  in tegra_dc_sor_detach()  local
980 	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);  in tegra_dc_sor_detach()
988 	tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);  in tegra_dc_sor_detach()
1004 	dc_int_mask = readl(&disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1005 	writel(0, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1008 	tegra_dc_sor_enable_sor(disp_ctrl, false);  in tegra_dc_sor_detach()
1009 	ret = tegra_dc_sor_general_act(disp_ctrl);  in tegra_dc_sor_detach()
1014 	writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_detach()
1015 	ret = tegra_dc_sor_general_act(disp_ctrl);  in tegra_dc_sor_detach()
1019 	tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);  in tegra_dc_sor_detach()
1021 	writel(dc_int_mask, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()