Lines Matching refs:DP_PADCTL
75 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
220 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
238 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_power_dplanes()
250 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
257 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_set_panel_power()
479 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
499 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_power_up()
598 DUMP_REG(DP_PADCTL(0)); in dump_sor_reg()
599 DUMP_REG(DP_PADCTL(1)); in dump_sor_reg()
848 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_set_lane_parm()
855 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); in tegra_dc_sor_set_lane_parm()
858 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); in tegra_dc_sor_set_lane_parm()
920 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
951 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
955 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()