Lines Matching full:sor
18 #include "sor.h"
51 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) in tegra_sor_readl() argument
53 return readl((u32 *)sor->base + reg); in tegra_sor_readl()
56 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, in tegra_sor_writel() argument
59 writel(val, (u32 *)sor->base + reg); in tegra_sor_writel()
62 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, in tegra_sor_write_field() argument
65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field()
68 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
73 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_disable_tx_pu() local
75 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
82 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_set_pe_vs_pc() local
84 tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); in tegra_dp_set_pe_vs_pc()
85 tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); in tegra_dp_set_pe_vs_pc()
87 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask, in tegra_dp_set_pe_vs_pc()
92 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, in tegra_dc_sor_poll_register() argument
101 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
115 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_power_state() local
119 orig_val = tegra_sor_readl(sor, PWR); in tegra_dc_sor_set_power_state()
128 tegra_sor_writel(sor, PWR, reg_val); in tegra_dc_sor_set_power_state()
131 if (tegra_dc_sor_poll_register(sor, PWR, in tegra_dc_sor_set_power_state()
146 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_dp_linkctl() local
149 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_dp_linkctl()
162 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_dp_linkctl()
166 tegra_sor_writel(sor, DP_TPG, 0x41414141); in tegra_dc_sor_set_dp_linkctl()
172 tegra_sor_writel(sor, DP_TPG, reg_val); in tegra_dc_sor_set_dp_linkctl()
175 tegra_sor_writel(sor, DP_TPG, 0x50505050); in tegra_dc_sor_set_dp_linkctl()
180 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, in tegra_dc_sor_enable_lane_sequencer() argument
185 /* SOR lane sequencer */ in tegra_dc_sor_enable_lane_sequencer()
201 tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); in tegra_dc_sor_enable_lane_sequencer()
203 if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, in tegra_dc_sor_enable_lane_sequencer()
207 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n"); in tegra_dc_sor_enable_lane_sequencer()
217 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_dplanes() local
220 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
238 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_power_dplanes()
242 return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); in tegra_dc_sor_power_dplanes()
247 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_panel_power() local
250 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
257 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_set_panel_power()
260 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, in tegra_dc_sor_config_pwm() argument
263 tegra_sor_writel(sor, PWM_DIV, pwm_div); in tegra_dc_sor_config_pwm()
264 tegra_sor_writel(sor, PWM_CTL, in tegra_dc_sor_config_pwm()
268 if (tegra_dc_sor_poll_register(sor, PWM_CTL, in tegra_dc_sor_config_pwm()
272 debug("dp: timeout while waiting for SOR PWM setting\n"); in tegra_dc_sor_config_pwm()
279 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_dp_mode() local
285 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); in tegra_dc_sor_set_dp_mode()
301 tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val); in tegra_dc_sor_set_dp_mode()
304 tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS, in tegra_dc_sor_set_dp_mode()
308 tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS, in tegra_dc_sor_set_dp_mode()
313 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor) in tegra_dc_sor_super_update() argument
315 tegra_sor_writel(sor, SUPER_STATE0, 0); in tegra_dc_sor_super_update()
316 tegra_sor_writel(sor, SUPER_STATE0, 1); in tegra_dc_sor_super_update()
317 tegra_sor_writel(sor, SUPER_STATE0, 0); in tegra_dc_sor_super_update()
320 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) in tegra_dc_sor_update() argument
322 tegra_sor_writel(sor, STATE0, 0); in tegra_dc_sor_update()
323 tegra_sor_writel(sor, STATE0, 1); in tegra_dc_sor_update()
324 tegra_sor_writel(sor, STATE0, 0); in tegra_dc_sor_update()
327 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) in tegra_dc_sor_io_set_dpd() argument
330 void *pmc_base = sor->pmc_base; in tegra_dc_sor_io_set_dpd()
375 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_internal_panel() local
378 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); in tegra_dc_sor_set_internal_panel()
386 tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); in tegra_dc_sor_set_internal_panel()
392 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_read_link_config() local
395 reg_val = tegra_sor_readl(sor, CLK_CNTRL); in tegra_dc_sor_read_link_config()
398 reg_val = tegra_sor_readl(sor, in tegra_dc_sor_read_link_config()
399 DP_LINKCTL(sor->portnum)); in tegra_dc_sor_read_link_config()
421 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_link_bandwidth() local
423 tegra_sor_write_field(sor, CLK_CNTRL, in tegra_dc_sor_set_link_bandwidth()
430 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_lane_count() local
433 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_lane_count()
452 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_lane_count()
456 * The SOR power sequencer does not work for t124 so SW has to
468 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_up() local
472 if (sor->power_is_up) in tegra_dc_sor_power_up()
479 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
489 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
496 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()
499 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_power_up()
504 ret = tegra_dc_sor_io_set_dpd(sor, 1); in tegra_dc_sor_power_up()
510 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
516 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()
521 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
527 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
531 sor->power_is_up = 1; in tegra_dc_sor_power_up()
537 static void dump_sor_reg(struct tegra_dc_sor_data *sor) in dump_sor_reg() argument
540 #a, a, tegra_sor_readl(sor, a)); in dump_sor_reg()
610 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, in tegra_dc_sor_config_panel() argument
633 tegra_sor_writel(sor, STATE1, reg_val); in tegra_dc_sor_config_panel()
644 tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), in tegra_dc_sor_config_panel()
650 tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), in tegra_dc_sor_config_panel()
656 tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), in tegra_dc_sor_config_panel()
662 tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), in tegra_dc_sor_config_panel()
667 tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); in tegra_dc_sor_config_panel()
669 tegra_sor_write_field(sor, CSTM, in tegra_dc_sor_config_panel()
676 tegra_dc_sor_config_pwm(sor, 1024, 1024); in tegra_dc_sor_config_panel()
695 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_enable_dp() local
698 tegra_sor_write_field(sor, CLK_CNTRL, in tegra_dc_sor_enable_dp()
702 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
707 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
710 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
716 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
723 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
726 if (tegra_dc_sor_poll_register(sor, PLL2, in tegra_dc_sor_enable_dp()
734 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | in tegra_dc_sor_enable_dp()
745 /* re-enable SOR clock */ in tegra_dc_sor_enable_dp()
761 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_attach() local
770 tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); in tegra_dc_sor_attach()
779 reg_val = tegra_sor_readl(sor, TEST); in tegra_dc_sor_attach()
783 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
788 * to clear sor internal valid signal. in tegra_dc_sor_attach()
796 tegra_dc_sor_update(sor); in tegra_dc_sor_attach()
797 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
799 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
803 tegra_dc_sor_super_update(sor); in tegra_dc_sor_attach()
813 if (tegra_dc_sor_poll_register(sor, TEST, in tegra_dc_sor_attach()
821 debug("%s: sor is attached\n", __func__); in tegra_dc_sor_attach()
825 dump_sor_reg(sor); in tegra_dc_sor_attach()
835 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_lane_parm() local
837 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), in tegra_dc_sor_set_lane_parm()
839 tegra_sor_writel(sor, PR(sor->portnum), in tegra_dc_sor_set_lane_parm()
841 tegra_sor_writel(sor, POSTCURSOR(sor->portnum), in tegra_dc_sor_set_lane_parm()
843 tegra_sor_writel(sor, LVDS, 0); in tegra_dc_sor_set_lane_parm()
848 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_set_lane_parm()
855 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); in tegra_dc_sor_set_lane_parm()
858 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); in tegra_dc_sor_set_lane_parm()
864 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_voltage_swing() local
878 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); in tegra_dc_sor_set_voltage_swing()
882 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); in tegra_dc_sor_set_voltage_swing()
883 tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); in tegra_dc_sor_set_voltage_swing()
891 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_down_unused_lanes() local
915 printf("Invalid sor lane count: %u\n", link_cfg->lane_count); in tegra_dc_sor_power_down_unused_lanes()
920 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
922 err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); in tegra_dc_sor_power_down_unused_lanes()
932 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_sor_precharge_lanes() local
951 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
955 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
972 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_detach() local
983 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | in tegra_dc_sor_detach()
986 tegra_dc_sor_super_update(sor); in tegra_dc_sor_detach()
990 if (tegra_dc_sor_poll_register(sor, TEST, in tegra_dc_sor_detach()
999 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | in tegra_dc_sor_detach()
1007 /* Stop DC->SOR path */ in tegra_dc_sor_detach()
1037 debug("sor: Cannot enable panel backlight\n"); in tegra_sor_set_backlight()
1071 { .compatible = "nvidia,tegra124-sor" },