Lines Matching defs:reg_val
65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local
96 u32 reg_val = 0; in tegra_dc_sor_poll_register() local
116 u32 reg_val; in tegra_dc_sor_set_power_state() local
147 u32 reg_val; in tegra_dc_sor_set_dp_linkctl() local
183 u32 reg_val; in tegra_dc_sor_enable_lane_sequencer() local
218 u32 reg_val; in tegra_dc_sor_power_dplanes() local
248 u32 reg_val; in tegra_dc_sor_set_panel_power() local
280 u32 reg_val; in tegra_dc_sor_set_dp_mode() local
329 u32 reg_val; in tegra_dc_sor_io_set_dpd() local
376 u32 reg_val; in tegra_dc_sor_set_internal_panel() local
393 u32 reg_val; in tegra_dc_sor_read_link_config() local
431 u32 reg_val; in tegra_dc_sor_set_lane_count() local
616 u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num; in tegra_dc_sor_config_panel() local
681 u32 reg_val = readl(&disp_ctrl->cmd.state_access); in tegra_dc_sor_enable_dc() local
763 u32 reg_val; in tegra_dc_sor_attach() local
964 u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_enable_sor() local