800 	u32 n_lanes = cfg->lane_count;  in tegra_dp_channel_eq_status()  local
805 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_channel_eq_status()
810 		if (n_lanes == 1) {  in tegra_dp_channel_eq_status()
844 	u32 n_lanes = cfg->lane_count;  in tegra_dp_clock_recovery_status()  local
848 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_clock_recovery_status()
854 		if (n_lanes == 1)  in tegra_dp_clock_recovery_status()
871 	u32 n_lanes = cfg->lane_count;  in tegra_dp_lt_adjust()  local
874 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_lt_adjust()
895 		for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_adjust()
915 static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes,  in tegra_dp_tpg()  argument
1012 	u32 n_lanes = cfg->lane_count;  in tegra_dp_lt_config()  local
1017 	for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_config()
1056 	for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_config()
1072 		for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_lt_config()
1095 				u32 n_lanes,  in _tegra_dp_channel_eq()  argument
1129 	u32 n_lanes = cfg->lane_count;  in tegra_dp_channel_eq()  local
1137 	tegra_dp_tpg(dp, tp_src, n_lanes, cfg);  in tegra_dp_channel_eq()
1139 	ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);  in tegra_dp_channel_eq()
1141 	tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);  in tegra_dp_channel_eq()
1148 				  u32 n_lanes,  in _tegra_dp_clk_recovery()  argument
1177 	u32 n_lanes = cfg->lane_count;  in tegra_dp_clk_recovery()  local
1181 	tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg);  in tegra_dp_clk_recovery()
1183 	err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes,  in tegra_dp_clk_recovery()
1186 		tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);  in tegra_dp_clk_recovery()