416 	const struct tegra_dp_link_config *link_cfg)  in tegra_dc_dp_dump_link_cfg()  argument
420 	      link_cfg->max_lane_count);  in tegra_dc_dp_dump_link_cfg()
422 	      link_cfg->support_enhanced_framing ? "Y" : "N");  in tegra_dc_dp_dump_link_cfg()
424 	      link_cfg->max_link_bw);  in tegra_dc_dp_dump_link_cfg()
426 	      link_cfg->bits_per_pixel);  in tegra_dc_dp_dump_link_cfg()
428 	      link_cfg->enhanced_framing ? "Y" : "N");  in tegra_dc_dp_dump_link_cfg()
430 	      link_cfg->scramble_ena ? "Y" : "N");  in tegra_dc_dp_dump_link_cfg()
432 	      link_cfg->link_bw);  in tegra_dc_dp_dump_link_cfg()
434 	      link_cfg->lane_count);  in tegra_dc_dp_dump_link_cfg()
436 	      link_cfg->activepolarity);  in tegra_dc_dp_dump_link_cfg()
438 	      link_cfg->active_count);  in tegra_dc_dp_dump_link_cfg()
440 	      link_cfg->tu_size);  in tegra_dc_dp_dump_link_cfg()
442 	      link_cfg->active_frac);  in tegra_dc_dp_dump_link_cfg()
444 	      link_cfg->watermark);  in tegra_dc_dp_dump_link_cfg()
446 	      link_cfg->hblank_sym);  in tegra_dc_dp_dump_link_cfg()
448 	      link_cfg->vblank_sym);  in tegra_dc_dp_dump_link_cfg()
486 				   struct tegra_dp_link_config *link_cfg)  in tegra_dc_dp_calc_config()  argument
488 	const u32	link_rate = 27 * link_cfg->link_bw * 1000 * 1000;  in tegra_dc_dp_calc_config()
510 	if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ ||  in tegra_dc_dp_calc_config()
511 	    !link_cfg->bits_per_pixel)  in tegra_dc_dp_calc_config()
514 	if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >=  in tegra_dc_dp_calc_config()
515 		(u64)link_rate * 8 * link_cfg->lane_count)  in tegra_dc_dp_calc_config()
521 	ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f;  in tegra_dc_dp_calc_config()
523 	do_div(ratio_f, link_rate * link_cfg->lane_count);  in tegra_dc_dp_calc_config()
586 		link_cfg->activepolarity = 0;  in tegra_dc_dp_calc_config()
587 		link_cfg->active_count   = lowest_neg_activepolarity ?  in tegra_dc_dp_calc_config()
589 		link_cfg->tu_size	      = lowest_neg_tusize;  in tegra_dc_dp_calc_config()
590 		link_cfg->active_frac    = 1;  in tegra_dc_dp_calc_config()
592 		link_cfg->activepolarity = lowest_neg_activepolarity;  in tegra_dc_dp_calc_config()
593 		link_cfg->active_count   = (u32)lowest_neg_activecount;  in tegra_dc_dp_calc_config()
594 		link_cfg->tu_size	      = lowest_neg_tusize;  in tegra_dc_dp_calc_config()
595 		link_cfg->active_frac    = (u32)lowest_neg_activefrac;  in tegra_dc_dp_calc_config()
598 	watermark_f = lldiv(ratio_f * link_cfg->tu_size * (f - ratio_f), f);  in tegra_dc_dp_calc_config()
599 	link_cfg->watermark = (u32)(lldiv(watermark_f + lowest_neg_error_f,  in tegra_dc_dp_calc_config()
600 		f)) + link_cfg->bits_per_pixel / 4 - 1;  in tegra_dc_dp_calc_config()
602 				link_cfg->bits_per_pixel) /  in tegra_dc_dp_calc_config()
603 			       (8 * link_cfg->lane_count);  in tegra_dc_dp_calc_config()
605 	if (link_cfg->watermark > 30) {  in tegra_dc_dp_calc_config()
607 		link_cfg->watermark = 30;  in tegra_dc_dp_calc_config()
609 	} else if (link_cfg->watermark > num_symbols_per_line) {  in tegra_dc_dp_calc_config()
611 		link_cfg->watermark = num_symbols_per_line;  in tegra_dc_dp_calc_config()
622 	link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ +  in tegra_dc_dp_calc_config()
625 			3 * link_cfg->enhanced_framing -  in tegra_dc_dp_calc_config()
626 			(12 / link_cfg->lane_count);  in tegra_dc_dp_calc_config()
628 	if (link_cfg->hblank_sym < 0)  in tegra_dc_dp_calc_config()
629 		link_cfg->hblank_sym = 0;  in tegra_dc_dp_calc_config()
639 	link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25)  in tegra_dc_dp_calc_config()
641 			link_cfg->lane_count) - 4;  in tegra_dc_dp_calc_config()
643 	if (link_cfg->vblank_sym < 0)  in tegra_dc_dp_calc_config()
644 		link_cfg->vblank_sym = 0;  in tegra_dc_dp_calc_config()
646 	link_cfg->is_valid = 1;  in tegra_dc_dp_calc_config()
648 	tegra_dc_dp_dump_link_cfg(dp, link_cfg);  in tegra_dc_dp_calc_config()
657 			struct tegra_dp_link_config *link_cfg)  in tegra_dc_dp_init_max_link_cfg()  argument
668 	link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK;  in tegra_dc_dp_init_max_link_cfg()
669 	link_cfg->tps3_supported = (dpcd_data &  in tegra_dc_dp_init_max_link_cfg()
672 	link_cfg->support_enhanced_framing =  in tegra_dc_dp_init_max_link_cfg()
679 	link_cfg->downspread = (dpcd_data & DP_MAX_DOWNSPREAD_VAL_0_5_PCT) ?  in tegra_dc_dp_init_max_link_cfg()
683 				    &link_cfg->aux_rd_interval);  in tegra_dc_dp_init_max_link_cfg()
687 				    &link_cfg->max_link_bw);  in tegra_dc_dp_init_max_link_cfg()
695 	link_cfg->drive_current = drive_current;  in tegra_dc_dp_init_max_link_cfg()
696 	link_cfg->preemphasis = preemphasis;  in tegra_dc_dp_init_max_link_cfg()
697 	link_cfg->postcursor = postcursor;  in tegra_dc_dp_init_max_link_cfg()
703 	link_cfg->alt_scramber_reset_cap =  in tegra_dc_dp_init_max_link_cfg()
706 	link_cfg->only_enhanced_framing =  in tegra_dc_dp_init_max_link_cfg()
710 	link_cfg->lane_count = link_cfg->max_lane_count;  in tegra_dc_dp_init_max_link_cfg()
711 	link_cfg->link_bw = link_cfg->max_link_bw;  in tegra_dc_dp_init_max_link_cfg()
712 	link_cfg->enhanced_framing = link_cfg->support_enhanced_framing;  in tegra_dc_dp_init_max_link_cfg()
713 	link_cfg->frame_in_ms = (1000 / 60) + 1;  in tegra_dc_dp_init_max_link_cfg()
715 	tegra_dc_dp_calc_config(dp, timing, link_cfg);  in tegra_dc_dp_init_max_link_cfg()
749 		const struct tegra_dp_link_config *link_cfg,  in tegra_dp_set_lane_count()  argument
756 	dpcd_data = link_cfg->lane_count;  in tegra_dp_set_lane_count()
757 	if (link_cfg->enhanced_framing)  in tegra_dp_set_lane_count()
763 	tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);  in tegra_dp_set_lane_count()
927 				const struct tegra_dp_link_config *link_cfg)  in tegra_dp_link_config()  argument
933 	if (link_cfg->lane_count == 0) {  in tegra_dp_link_config()
960 	if (link_cfg->alt_scramber_reset_cap) {  in tegra_dp_link_config()
966 	ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);  in tegra_dp_link_config()
971 	ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);  in tegra_dp_link_config()
977 				    link_cfg);  in tegra_dp_link_config()
1237 		const struct tegra_dp_link_config *link_cfg,  in tegra_dc_dp_fast_link_training()  argument
1247 	u32	mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);  in tegra_dc_dp_fast_link_training()
1249 	tegra_dc_sor_set_lane_parm(sor, link_cfg);  in tegra_dc_dp_fast_link_training()
1254 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);  in tegra_dc_dp_fast_link_training()
1258 	for (j = 0; j < link_cfg->lane_count; ++j)  in tegra_dc_dp_fast_link_training()
1273 	tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena);  in tegra_dc_dp_fast_link_training()
1274 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);  in tegra_dc_dp_fast_link_training()
1277 			       link_cfg->link_bw == 20 ? 0x23 : 0x22);  in tegra_dc_dp_fast_link_training()
1278 	for (j = 0; j < link_cfg->lane_count; ++j)  in tegra_dc_dp_fast_link_training()
1291 				    link_cfg);  in tegra_dc_dp_fast_link_training()
1294 	if (tegra_dc_dp_link_trained(dp, link_cfg)) {  in tegra_dc_dp_fast_link_training()
1302 	      link_cfg->link_bw, link_cfg->lane_count);  in tegra_dc_dp_fast_link_training()
1308 		struct tegra_dp_link_config *link_cfg,  in tegra_dp_do_link_training()  argument
1317 		ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);  in tegra_dp_do_link_training()
1325 			ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);  in tegra_dp_do_link_training()
1334 		ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg);  in tegra_dp_do_link_training()
1344 	if ((link_cfg->link_bw == link_bw) &&  in tegra_dp_do_link_training()
1345 	    (link_cfg->lane_count == lane_count))  in tegra_dp_do_link_training()
1352 			struct tegra_dp_link_config *link_cfg,  in tegra_dc_dp_explore_link_cfg()  argument
1363 	if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) {  in tegra_dc_dp_explore_link_cfg()
1368 	link_cfg->is_valid = 0;  in tegra_dc_dp_explore_link_cfg()
1370 	memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg));  in tegra_dc_dp_explore_link_cfg()
1382 		memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg));  in tegra_dc_dp_explore_link_cfg()
1384 	return link_cfg->is_valid ? 0 : -EFAULT;  in tegra_dc_dp_explore_link_cfg()
1426 				  struct tegra_dp_link_config *link_cfg,  in tegra_dc_dp_check_sink()  argument
1444 		if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms *  in tegra_dc_dp_check_sink()
1456 		if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,  in tegra_dc_dp_check_sink()
1463 		tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);  in tegra_dc_dp_check_sink()
1475 	struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg;  in tegra_dp_enable()  local
1481 	memset(link_cfg, '\0', sizeof(*link_cfg));  in tegra_dp_enable()
1482 	link_cfg->is_valid = 0;  in tegra_dp_enable()
1483 	link_cfg->scramble_ena = 1;  in tegra_dp_enable()
1492 	link_cfg->bits_per_pixel = panel_bpp;  in tegra_dp_enable()
1493 	if (tegra_dc_dp_init_max_link_cfg(timing, priv, link_cfg)) {  in tegra_dp_enable()
1504 	ret = tegra_dc_sor_enable_dp(sor, link_cfg);  in tegra_dp_enable()
1536 	if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) {  in tegra_dp_enable()
1542 	ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);  in tegra_dp_enable()
1551 		ret = tegra_dc_dp_check_sink(priv, link_cfg, timing);  in tegra_dp_enable()
1557 	tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);  in tegra_dp_enable()