95 					  u32 *aux_stat)  in tegra_dc_dpaux_write_chunk()  argument
141 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_write_chunk()
143 		if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||  in tegra_dc_dpaux_write_chunk()
144 		    (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||  in tegra_dc_dpaux_write_chunk()
145 		    (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||  in tegra_dc_dpaux_write_chunk()
146 		    (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {  in tegra_dc_dpaux_write_chunk()
149 				      *aux_stat, timeout_retries);  in tegra_dc_dpaux_write_chunk()
152 						   *aux_stat);  in tegra_dc_dpaux_write_chunk()
156 				      *aux_stat);  in tegra_dc_dpaux_write_chunk()
161 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||  in tegra_dc_dpaux_write_chunk()
162 		    (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {  in tegra_dc_dpaux_write_chunk()
165 				      *aux_stat, defer_retries);  in tegra_dc_dpaux_write_chunk()
168 						   *aux_stat);  in tegra_dc_dpaux_write_chunk()
172 				      *aux_stat);  in tegra_dc_dpaux_write_chunk()
177 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==  in tegra_dc_dpaux_write_chunk()
179 			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);  in tegra_dc_dpaux_write_chunk()
182 			debug("dp: aux write failed (0x%x)\n", *aux_stat);  in tegra_dc_dpaux_write_chunk()
192 					 u32 *aux_stat)  in tegra_dc_dpaux_read_chunk()  argument
215 	*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_read_chunk()
216 	if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {  in tegra_dc_dpaux_read_chunk()
239 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_read_chunk()
241 		if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||  in tegra_dc_dpaux_read_chunk()
242 		    (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||  in tegra_dc_dpaux_read_chunk()
243 		    (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||  in tegra_dc_dpaux_read_chunk()
244 		    (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {  in tegra_dc_dpaux_read_chunk()
247 				      *aux_stat, timeout_retries);  in tegra_dc_dpaux_read_chunk()
250 						   *aux_stat);  in tegra_dc_dpaux_read_chunk()
254 				      *aux_stat);  in tegra_dc_dpaux_read_chunk()
259 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||  in tegra_dc_dpaux_read_chunk()
260 		    (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {  in tegra_dc_dpaux_read_chunk()
263 				      *aux_stat, defer_retries);  in tegra_dc_dpaux_read_chunk()
266 						   *aux_stat);  in tegra_dc_dpaux_read_chunk()
270 				      *aux_stat);  in tegra_dc_dpaux_read_chunk()
275 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==  in tegra_dc_dpaux_read_chunk()
284 			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);  in tegra_dc_dpaux_read_chunk()
289 			debug("dp: aux read failed (0x%x\n", *aux_stat);  in tegra_dc_dpaux_read_chunk()
300 			u8 *data, u32 *size, u32 *aux_stat)  in tegra_dc_dpaux_read()  argument
312 						data, &cur_size, aux_stat);  in tegra_dc_dpaux_read()
362 				 u8 addr, u8 *data, u32 size, u32 *aux_stat)  in tegra_dc_i2c_aux_read()  argument
373 				&addr, &len, aux_stat);  in tegra_dc_i2c_aux_read()
382 				data, &cur_size, aux_stat);  in tegra_dc_i2c_aux_read()
1583 	u32 aux_stat = 0;  in tegra_dp_read_edid()  local
1588 				     buf_size, &aux_stat);  in tegra_dp_read_edid()