18 #include "sor.h"
35 	struct udevice *sor;  member
606 		debug("dp: sor setting: unable to get a good tusize, force watermark to 30\n");  in tegra_dc_dp_calc_config()
610 		debug("dp: sor setting: force watermark to the number of symbols in the line\n");  in tegra_dc_dp_calc_config()
720 				struct udevice *sor, int ena)  in tegra_dc_dp_set_assr()  argument
734 	tegra_dc_sor_set_internal_panel(sor, ena);  in tegra_dc_dp_set_assr()
739 				       struct udevice *sor,  in tegra_dp_set_link_bandwidth()  argument
742 	tegra_dc_sor_set_link_bandwidth(sor, link_bw);  in tegra_dp_set_link_bandwidth()
750 		struct udevice *sor)  in tegra_dp_set_lane_count()  argument
763 	tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);  in tegra_dp_set_lane_count()
922 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg);  in tegra_dp_tpg()
961 		ret = tegra_dc_dp_set_assr(dp, dp->sor, 1);  in tegra_dp_link_config()
966 	ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);  in tegra_dp_link_config()
971 	ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);  in tegra_dp_link_config()
976 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none,  in tegra_dp_link_config()
1011 	struct udevice *sor = dp->sor;  in tegra_dp_lt_config()  local
1048 		tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift,  in tegra_dp_lt_config()
1053 	tegra_dp_disable_tx_pu(dp->sor);  in tegra_dp_lt_config()
1195 	struct udevice *sor = dp->sor;  in tegra_dc_dp_full_link_training()  local
1199 	tegra_sor_precharge_lanes(sor, cfg);  in tegra_dc_dp_full_link_training()
1238 		struct udevice *sor)  in tegra_dc_dp_fast_link_training()  argument
1249 	tegra_dc_sor_set_lane_parm(sor, link_cfg);  in tegra_dc_dp_fast_link_training()
1254 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);  in tegra_dc_dp_fast_link_training()
1273 	tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena);  in tegra_dc_dp_fast_link_training()
1274 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);  in tegra_dc_dp_fast_link_training()
1290 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,  in tegra_dc_dp_fast_link_training()
1295 		tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dc_dp_fast_link_training()
1310 		struct udevice *sor)  in tegra_dp_do_link_training()  argument
1317 		ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);  in tegra_dp_do_link_training()
1325 			ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);  in tegra_dp_do_link_training()
1342 	tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dp_do_link_training()
1353 			struct udevice *sor,  in tegra_dc_dp_explore_link_cfg()  argument
1380 		(!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor)))  in tegra_dc_dp_explore_link_cfg()
1453 		ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);  in tegra_dc_dp_check_sink()
1456 		if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,  in tegra_dc_dp_check_sink()
1462 		tegra_dc_sor_set_power_state(dp->sor, 1);  in tegra_dc_dp_check_sink()
1463 		tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);  in tegra_dc_dp_check_sink()
1476 	struct udevice *sor;  in tegra_dp_enable()  local
1498 	ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);  in tegra_dp_enable()
1499 	if (ret || !sor) {  in tegra_dp_enable()
1500 		debug("dp: failed to find SOR device: ret=%d\n", ret);  in tegra_dp_enable()
1503 	priv->sor = sor;  in tegra_dp_enable()
1504 	ret = tegra_dc_sor_enable_dp(sor, link_cfg);  in tegra_dp_enable()
1508 	tegra_dc_sor_set_panel_power(sor, 1);  in tegra_dp_enable()
1536 	if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) {  in tegra_dp_enable()
1541 	tegra_dc_sor_set_power_state(sor, 1);  in tegra_dp_enable()
1542 	ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);  in tegra_dp_enable()
1557 	tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);  in tegra_dp_enable()
1559 	ret = video_bridge_set_backlight(sor, 80);  in tegra_dp_enable()