865 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_lt_adjust()
881 		vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>  in tegra_dp_lt_adjust()
886 		vs[1 + 2 * cnt] =  in tegra_dp_lt_adjust()
1008 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_lt_config()
1044 		pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1045 		vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1046 		pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1057 		u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);  in tegra_dp_lt_config()
1058 		u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);  in tegra_dp_lt_config()
1060 		val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) |  in tegra_dp_lt_config()
1094 				u32 vs[4], u32 pc[4], u8 pc_supported,  in _tegra_dp_channel_eq()
1104 			ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported,  in _tegra_dp_channel_eq()
1108 			tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_channel_eq()
1125 static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_channel_eq()
1139 	ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);  in tegra_dp_channel_eq()
1147 				  u32 vs[4], u32 pc[4], u8 pc_supported,  in _tegra_dp_clk_recovery()
1155 		tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_clk_recovery()
1161 		memcpy(vs_temp, vs, sizeof(vs_temp));  in _tegra_dp_clk_recovery()
1162 		tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg);  in _tegra_dp_clk_recovery()
1164 		if (memcmp(vs_temp, vs, sizeof(vs_temp)))  in _tegra_dp_clk_recovery()
1168 	} while (retry_cnt < 5);  in _tegra_dp_clk_recovery()
1174 				 u32 vs[4], u32 pc[4],  in tegra_dp_clk_recovery()
1183 	err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes,  in tegra_dp_clk_recovery()
1197 	u32 pe[4], vs[4], pc[4];  in tegra_dc_dp_full_link_training()  local
1203 	memset(vs, DRIVECURRENT_LEVEL0, sizeof(vs));  in tegra_dc_dp_full_link_training()
1206 	err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()
1215 	err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()
1429 	const int max_retry = 5;  in tegra_dc_dp_check_sink()
1436 	 * from 5  in tegra_dc_dp_check_sink()
1438 	delay_frame = 5;  in tegra_dc_dp_check_sink()