Lines Matching +full:5 +full:vs
33 #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12)
55 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20)
107 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8)
293 static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) in tegra_dp_is_max_vs() argument
295 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; in tegra_dp_is_max_vs()
298 static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) in tegra_dp_is_max_pe() argument
300 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; in tegra_dp_is_max_pe()
328 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
329 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
340 #define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5)
341 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
342 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
368 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
369 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
370 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
391 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
392 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
393 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)