Lines Matching +full:timing +full:-
4 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/arch-tegra/dc.h>
22 #include <dm/uclass-internal.h>
28 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
46 static void print_mode(const struct display_timing *timing) in print_mode() argument
48 int refresh = tegra_dc_calc_refresh(timing); in print_mode()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
56 const struct display_timing *timing, in update_display_mode() argument
59 print_mode(timing); in update_display_mode()
61 writel(0x1, &disp_ctrl->disp.disp_timing_opt); in update_display_mode()
64 &disp_ctrl->disp.ref_to_sync); in update_display_mode()
66 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
67 &disp_ctrl->disp.sync_width); in update_display_mode()
69 writel(((timing->vback_porch.typ - vref_to_sync) << 16) | in update_display_mode()
70 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); in update_display_mode()
72 writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | in update_display_mode()
73 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); in update_display_mode()
75 writel(timing->hactive.typ | (timing->vactive.typ << 16), in update_display_mode()
76 &disp_ctrl->disp.disp_active); in update_display_mode()
92 ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, in update_display_mode()
93 &disp_ctrl->disp.disp_clk_ctrl); in update_display_mode()
95 timing->pixelclock.typ, shift_clock_div); in update_display_mode()
109 timeout_us -= poll_interval_us; in tegra_dc_poll_register()
122 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); in tegra_dc_sor_general_act()
124 if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, in tegra_dc_sor_general_act()
128 return -ETIMEDOUT; in tegra_dc_sor_general_act()
152 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_disable_win_short_raster()
156 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_disable_win_short_raster()
157 dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt); in tegra_dc_sor_disable_win_short_raster()
158 writel(0, &disp_ctrl->win.win_opt); in tegra_dc_sor_disable_win_short_raster()
159 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); in tegra_dc_sor_disable_win_short_raster()
162 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_disable_win_short_raster()
165 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); in tegra_dc_sor_disable_win_short_raster()
167 &disp_ctrl->disp.ref_to_sync); in tegra_dc_sor_disable_win_short_raster()
169 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); in tegra_dc_sor_disable_win_short_raster()
171 &disp_ctrl->disp.sync_width); in tegra_dc_sor_disable_win_short_raster()
173 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch); in tegra_dc_sor_disable_win_short_raster()
175 &disp_ctrl->disp.back_porch); in tegra_dc_sor_disable_win_short_raster()
177 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch); in tegra_dc_sor_disable_win_short_raster()
179 &disp_ctrl->disp.front_porch); in tegra_dc_sor_disable_win_short_raster()
181 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active); in tegra_dc_sor_disable_win_short_raster()
183 &disp_ctrl->disp.disp_active); in tegra_dc_sor_disable_win_short_raster()
185 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); in tegra_dc_sor_disable_win_short_raster()
194 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_restore_win_and_raster()
197 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_restore_win_and_raster()
198 writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt); in tegra_dc_sor_restore_win_and_raster()
199 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); in tegra_dc_sor_restore_win_and_raster()
202 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); in tegra_dc_sor_restore_win_and_raster()
204 writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); in tegra_dc_sor_restore_win_and_raster()
205 writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); in tegra_dc_sor_restore_win_and_raster()
206 writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); in tegra_dc_sor_restore_win_and_raster()
207 writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); in tegra_dc_sor_restore_win_and_raster()
208 writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); in tegra_dc_sor_restore_win_and_raster()
210 writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); in tegra_dc_sor_restore_win_and_raster()
222 return -1; in tegra_depth_for_bpp()
228 const struct display_timing *timing) in update_window() argument
234 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); in update_window()
236 writel(((timing->vactive.typ << 16) | timing->hactive.typ), in update_window()
237 &disp_ctrl->win.size); in update_window()
238 writel(((timing->vactive.typ << 16) | in update_window()
239 (timing->hactive.typ * fb_bits_per_pixel / 8)), in update_window()
240 &disp_ctrl->win.prescaled_size); in update_window()
241 writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / in update_window()
242 32 * 32), &disp_ctrl->win.line_stride); in update_window()
245 if (colour_depth == -1) in update_window()
246 return -EINVAL; in update_window()
248 writel(colour_depth, &disp_ctrl->win.color_depth); in update_window()
250 writel(frame_buffer, &disp_ctrl->winbuf.start_addr); in update_window()
252 &disp_ctrl->win.dda_increment); in update_window()
254 writel(colour_white, &disp_ctrl->disp.blend_background_color); in update_window()
256 &disp_ctrl->cmd.disp_cmd); in update_window()
258 writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); in update_window()
262 writel(val, &disp_ctrl->cmd.state_ctrl); in update_window()
265 val = readl(&disp_ctrl->win.win_opt); in update_window()
266 writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); in update_window()
274 writel(0x00000000, &disp_ctrl->cmd.int_mask); in tegra_dc_init()
276 &disp_ctrl->cmd.state_access); in tegra_dc_init()
277 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); in tegra_dc_init()
278 writel(0x00000000, &disp_ctrl->win.win_opt); in tegra_dc_init()
279 writel(0x00000000, &disp_ctrl->win.byte_swap); in tegra_dc_init()
280 writel(0x00000000, &disp_ctrl->win.buffer_ctrl); in tegra_dc_init()
282 writel(0x00000000, &disp_ctrl->win.pos); in tegra_dc_init()
283 writel(0x00000000, &disp_ctrl->win.h_initial_dda); in tegra_dc_init()
284 writel(0x00000000, &disp_ctrl->win.v_initial_dda); in tegra_dc_init()
285 writel(0x00000000, &disp_ctrl->win.dda_increment); in tegra_dc_init()
286 writel(0x00000000, &disp_ctrl->win.dv_ctrl); in tegra_dc_init()
288 writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); in tegra_dc_init()
289 writel(0x00000000, &disp_ctrl->win.blend_match_select); in tegra_dc_init()
290 writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); in tegra_dc_init()
291 writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); in tegra_dc_init()
293 writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); in tegra_dc_init()
294 writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); in tegra_dc_init()
295 writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); in tegra_dc_init()
297 writel(0x00000000, &disp_ctrl->com.crc_checksum); in tegra_dc_init()
298 writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); in tegra_dc_init()
299 writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); in tegra_dc_init()
300 writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); in tegra_dc_init()
301 writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); in tegra_dc_init()
302 writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); in tegra_dc_init()
307 static void dump_config(int panel_bpp, struct display_timing *timing) in dump_config() argument
309 printf("timing->hactive.typ = %d\n", timing->hactive.typ); in dump_config()
310 printf("timing->vactive.typ = %d\n", timing->vactive.typ); in dump_config()
311 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); in dump_config()
313 printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); in dump_config()
314 printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); in dump_config()
315 printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); in dump_config()
317 printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); in dump_config()
318 printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); in dump_config()
319 printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); in dump_config()
326 struct display_timing *timing) in display_update_config_from_edid() argument
328 return display_read_timing(dp_dev, timing); in display_update_config_from_edid()
332 int fb_bits_per_pixel, struct display_timing *timing) in display_init() argument
349 dev->name, ret); in display_init()
354 debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name, in display_init()
356 disp_uc_plat->src_dev = dev; in display_init()
365 if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { in display_init()
366 debug("%s: Failed to decode display timing\n", __func__); in display_init()
367 return -EINVAL; in display_init()
370 ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); in display_init()
373 dump_config(panel_bpp, timing); in display_init()
381 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); in display_init()
384 return -EIO; in display_init()
385 } else if (plld_rate != timing->pixelclock.typ * 2) { in display_init()
387 timing->pixelclock.typ = plld_rate / 2; in display_init()
398 ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); in display_init()
405 ret = display_enable(dp_dev, panel_bpp, timing); in display_init()
411 ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); in display_init()
432 struct display_timing timing; in tegra124_lcd_init() local
451 ret = display_init(dev, lcdbase, 1 << l2bpp, &timing); in tegra124_lcd_init()
455 uc_priv->xsize = roundup(timing.hactive.typ, 16); in tegra124_lcd_init()
456 uc_priv->ysize = timing.vactive.typ; in tegra124_lcd_init()
457 uc_priv->bpix = l2bpp; in tegra124_lcd_init()
473 ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16); in tegra124_lcd_probe()
486 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * in tegra124_lcd_bind()
488 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); in tegra124_lcd_bind()
494 { .compatible = "nvidia,tegra124-dc" },
499 .name = "tegra124-dc",