Lines Matching +full:panel +full:- +full:timing
3 * SPDX-License-Identifier: GPL-2.0+
9 #include <panel.h>
21 #include <asm/arch-tegra/timer.h>
30 struct display_timing timing; member
31 struct udevice *panel; member
49 val = readl(&dc->cmd.disp_win_header); in update_window()
51 writel(val, &dc->cmd.disp_win_header); in update_window()
53 writel(win->fmt, &dc->win.color_depth); in update_window()
55 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, in update_window()
58 val = win->out_x << H_POSITION_SHIFT; in update_window()
59 val |= win->out_y << V_POSITION_SHIFT; in update_window()
60 writel(val, &dc->win.pos); in update_window()
62 val = win->out_w << H_SIZE_SHIFT; in update_window()
63 val |= win->out_h << V_SIZE_SHIFT; in update_window()
64 writel(val, &dc->win.size); in update_window()
66 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; in update_window()
67 val |= win->h << V_PRESCALED_SIZE_SHIFT; in update_window()
68 writel(val, &dc->win.prescaled_size); in update_window()
70 writel(0, &dc->win.h_initial_dda); in update_window()
71 writel(0, &dc->win.v_initial_dda); in update_window()
73 h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); in update_window()
74 v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); in update_window()
78 writel(val, &dc->win.dda_increment); in update_window()
80 writel(win->stride, &dc->win.line_stride); in update_window()
81 writel(0, &dc->win.buf_stride); in update_window()
84 if (win->bpp < 24) in update_window()
86 writel(val, &dc->win.win_opt); in update_window()
88 writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); in update_window()
89 writel(win->x, &dc->winbuf.addr_h_offset); in update_window()
90 writel(win->y, &dc->winbuf.addr_v_offset); in update_window()
92 writel(0xff00, &dc->win.blend_nokey); in update_window()
93 writel(0xff00, &dc->win.blend_1win); in update_window()
97 writel(val, &dc->cmd.state_ctrl); in update_window()
103 struct display_timing *dt = &priv->timing; in update_display_mode()
108 writel(0x0, &disp->disp_timing_opt); in update_display_mode()
110 writel(1 | 1 << 16, &disp->ref_to_sync); in update_display_mode()
111 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); in update_display_mode()
112 writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, in update_display_mode()
113 &disp->back_porch); in update_display_mode()
114 writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, in update_display_mode()
115 &disp->front_porch); in update_display_mode()
116 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); in update_display_mode()
120 writel(val, &disp->data_enable_opt); in update_display_mode()
125 writel(val, &disp->disp_interface_ctrl); in update_display_mode()
134 div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; in update_display_mode()
137 writel(0x00010001, &disp->shift_clk_opt); in update_display_mode()
141 writel(val, &disp->disp_clk_ctrl); in update_display_mode()
151 writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); in basic_init()
152 writel(0x0000011a, &cmd->cont_syncpt_vsync); in basic_init()
153 writel(0x00000000, &cmd->int_type); in basic_init()
154 writel(0x00000000, &cmd->int_polarity); in basic_init()
155 writel(0x00000000, &cmd->int_mask); in basic_init()
156 writel(0x00000000, &cmd->int_enb); in basic_init()
161 writel(val, &cmd->disp_pow_ctrl); in basic_init()
163 val = readl(&cmd->disp_cmd); in basic_init()
165 writel(val, &cmd->disp_cmd); in basic_init()
170 writel(0x00000020, &disp->mem_high_pri); in basic_init_timer()
171 writel(0x00000001, &disp->mem_high_pri_timer); in basic_init_timer()
210 writel(rgb_enb_tab[i], &com->pin_output_enb[i]); in rgb_enable()
211 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); in rgb_enable()
212 writel(rgb_data_tab[i], &com->pin_output_data[i]); in rgb_enable()
216 writel(rgb_sel_tab[i], &com->pin_output_sel[i]); in rgb_enable()
222 win->x = 0; in setup_window()
223 win->y = 0; in setup_window()
224 win->w = priv->width; in setup_window()
225 win->h = priv->height; in setup_window()
226 win->out_x = 0; in setup_window()
227 win->out_y = 0; in setup_window()
228 win->out_w = priv->width; in setup_window()
229 win->out_h = priv->height; in setup_window()
230 win->phys_addr = priv->frame_buffer; in setup_window()
231 win->stride = priv->width * (1 << priv->log2_bpp) / 8; in setup_window()
232 debug("%s: depth = %d\n", __func__, priv->log2_bpp); in setup_window()
233 switch (priv->log2_bpp) { in setup_window()
235 win->fmt = COLOR_DEPTH_R8G8B8A8; in setup_window()
236 win->bpp = 32; in setup_window()
239 win->fmt = COLOR_DEPTH_B5G6R5; in setup_window()
240 win->bpp = 16; in setup_window()
245 return -1; in setup_window()
254 * The frame buffer can be positioned by U-Boot or overridden by the fdt.
255 * You should pass in the U-Boot address here, and check the contents of
261 * @return 0 if ok, -1 on error (unsupported bits per pixel)
269 priv->frame_buffer = (u32)default_lcd_base; in tegra_display_probe()
271 dc = (struct dc_ctlr *)priv->disp; in tegra_display_probe()
282 basic_init(&dc->cmd); in tegra_display_probe()
283 basic_init_timer(&dc->disp); in tegra_display_probe()
284 rgb_enable(&dc->com); in tegra_display_probe()
286 if (priv->pixel_clock) in tegra_display_probe()
287 update_display_mode(&dc->disp, priv); in tegra_display_probe()
290 return -1; in tegra_display_probe()
302 const void *blob = gd->fdt_blob; in tegra_lcd_probe()
307 if (tegra_display_probe(blob, priv, (void *)plat->base)) { in tegra_lcd_probe()
309 return -1; in tegra_lcd_probe()
315 ret = panel_enable_backlight(priv->panel); in tegra_lcd_probe()
321 mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, in tegra_lcd_probe()
327 uc_priv->xsize = priv->width; in tegra_lcd_probe()
328 uc_priv->ysize = priv->height; in tegra_lcd_probe()
329 uc_priv->bpix = priv->log2_bpp; in tegra_lcd_probe()
330 debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer, in tegra_lcd_probe()
331 plat->size); in tegra_lcd_probe()
339 const void *blob = gd->fdt_blob; in tegra_lcd_ofdata_to_platdata()
340 struct display_timing *timing; in tegra_lcd_ofdata_to_platdata() local
346 priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev); in tegra_lcd_ofdata_to_platdata()
347 if (!priv->disp) { in tegra_lcd_ofdata_to_platdata()
349 return -EINVAL; in tegra_lcd_ofdata_to_platdata()
355 __func__, dev->name, rgb); in tegra_lcd_ofdata_to_platdata()
356 return -EINVAL; in tegra_lcd_ofdata_to_platdata()
359 ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); in tegra_lcd_ofdata_to_platdata()
361 debug("%s: Cannot read display timing for '%s' (ret=%d)\n", in tegra_lcd_ofdata_to_platdata()
362 __func__, dev->name, ret); in tegra_lcd_ofdata_to_platdata()
363 return -EINVAL; in tegra_lcd_ofdata_to_platdata()
365 timing = &priv->timing; in tegra_lcd_ofdata_to_platdata()
366 priv->width = timing->hactive.typ; in tegra_lcd_ofdata_to_platdata()
367 priv->height = timing->vactive.typ; in tegra_lcd_ofdata_to_platdata()
368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
369 priv->log2_bpp = VIDEO_BPP16; in tegra_lcd_ofdata_to_platdata()
372 * Sadly the panel phandle is in an rgb subnode so we cannot use in tegra_lcd_ofdata_to_platdata()
375 panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); in tegra_lcd_ofdata_to_platdata()
377 debug("%s: Cannot find panel information\n", __func__); in tegra_lcd_ofdata_to_platdata()
378 return -EINVAL; in tegra_lcd_ofdata_to_platdata()
381 &priv->panel); in tegra_lcd_ofdata_to_platdata()
383 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, in tegra_lcd_ofdata_to_platdata()
384 dev->name, ret); in tegra_lcd_ofdata_to_platdata()
394 const void *blob = gd->fdt_blob; in tegra_lcd_bind()
400 return -ENODEV; in tegra_lcd_bind()
402 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * in tegra_lcd_bind()
412 { .compatible = "nvidia,tegra20-dc" },