Lines Matching +full:de +full:- +full:serializer
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
82 return -ETIME; in await_completion()
100 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_hdmi_hpd_detect()
105 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
107 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
110 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
112 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); in sunxi_hdmi_hpd_detect()
113 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0); in sunxi_hdmi_hpd_detect()
116 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) in sunxi_hdmi_hpd_detect()
130 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE); in sunxi_hdmi_shutdown()
131 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_shutdown()
132 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_shutdown()
134 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_shutdown()
144 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR); in sunxi_hdmi_ddc_do_command()
148 SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr); in sunxi_hdmi_ddc_do_command()
150 writel(n, &hdmi->ddc_byte_count); in sunxi_hdmi_ddc_do_command()
151 writel(cmnd, &hdmi->ddc_cmnd); in sunxi_hdmi_ddc_do_command()
153 writel(n << 16 | cmnd, &hdmi->ddc_cmnd); in sunxi_hdmi_ddc_do_command()
155 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); in sunxi_hdmi_ddc_do_command()
157 return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0); in sunxi_hdmi_ddc_do_command()
175 return -ETIME; in sunxi_hdmi_ddc_read()
178 *buf++ = readb(&hdmi->ddc_fifo_data); in sunxi_hdmi_ddc_read()
181 count -= n; in sunxi_hdmi_ddc_read()
200 } while (r && retries--); in sunxi_hdmi_edid_get_block()
219 &hdmi->pad_ctrl1); in sunxi_hdmi_edid_get_mode()
221 &hdmi->pll_ctrl); in sunxi_hdmi_edid_get_mode()
222 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); in sunxi_hdmi_edid_get_mode()
225 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
229 SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl); in sunxi_hdmi_edid_get_mode()
230 if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0)) in sunxi_hdmi_edid_get_mode()
231 return -EIO; in sunxi_hdmi_edid_get_mode()
233 writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock); in sunxi_hdmi_edid_get_mode()
236 SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl); in sunxi_hdmi_edid_get_mode()
244 r = -EINVAL; in sunxi_hdmi_edid_get_mode()
261 clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE); in sunxi_hdmi_edid_get_mode()
262 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
272 return -EINVAL; in sunxi_hdmi_edid_get_mode()
283 return -ENOENT; in sunxi_hdmi_edid_get_mode()
305 * deep enough fifo-s causing flickering / tearing in full-hd mode due to
307 * dma from memory, as the frontend does have deep enough fifo-s.
349 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
350 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
351 clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000); in sunxi_frontend_init()
353 setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); in sunxi_frontend_init()
356 writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]); in sunxi_frontend_init()
357 writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]); in sunxi_frontend_init()
358 writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]); in sunxi_frontend_init()
359 writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]); in sunxi_frontend_init()
360 writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]); in sunxi_frontend_init()
361 writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]); in sunxi_frontend_init()
364 setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY); in sunxi_frontend_init()
373 setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS); in sunxi_frontend_mode_set()
374 writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); in sunxi_frontend_mode_set()
375 writel(mode->xres * 4, &de_fe->ch0_stride); in sunxi_frontend_mode_set()
376 writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt); in sunxi_frontend_mode_set()
377 writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt); in sunxi_frontend_mode_set()
379 writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), in sunxi_frontend_mode_set()
380 &de_fe->ch0_insize); in sunxi_frontend_mode_set()
381 writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), in sunxi_frontend_mode_set()
382 &de_fe->ch0_outsize); in sunxi_frontend_mode_set()
383 writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact); in sunxi_frontend_mode_set()
384 writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact); in sunxi_frontend_mode_set()
386 writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), in sunxi_frontend_mode_set()
387 &de_fe->ch1_insize); in sunxi_frontend_mode_set()
388 writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), in sunxi_frontend_mode_set()
389 &de_fe->ch1_outsize); in sunxi_frontend_mode_set()
390 writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact); in sunxi_frontend_mode_set()
391 writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact); in sunxi_frontend_mode_set()
393 setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY); in sunxi_frontend_mode_set()
401 setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START); in sunxi_frontend_enable()
431 * Allwinner calls it the back-end, but i like composer better.
445 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); in sunxi_composer_init()
449 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0); in sunxi_composer_init()
451 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0); in sunxi_composer_init()
453 clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000); in sunxi_composer_init()
459 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE); in sunxi_composer_init()
477 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), in sunxi_composer_mode_set()
478 &de_be->disp_size); in sunxi_composer_mode_set()
479 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), in sunxi_composer_mode_set()
480 &de_be->layer0_size); in sunxi_composer_mode_set()
482 writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride); in sunxi_composer_mode_set()
483 writel(address << 3, &de_be->layer0_addr_low32b); in sunxi_composer_mode_set()
484 writel(address >> 29, &de_be->layer0_addr_high4b); in sunxi_composer_mode_set()
486 writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl); in sunxi_composer_mode_set()
488 writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl); in sunxi_composer_mode_set()
490 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); in sunxi_composer_mode_set()
491 if (mode->vmode == FB_VMODE_INTERLACED) in sunxi_composer_mode_set()
492 setbits_le32(&de_be->mode, in sunxi_composer_mode_set()
500 &de_be->output_color_ctrl); in sunxi_composer_mode_set()
503 &de_be->output_color_coef[i]); in sunxi_composer_mode_set()
514 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()
515 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); in sunxi_composer_enable()
519 * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
554 diff = dotclock - value; in sunxi_lcdc_pll_set()
570 diff = dotclock - value; in sunxi_lcdc_pll_set()
616 &ccm->lcd0_ch0_clk_cfg); in sunxi_lcdc_pll_set()
621 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg); in sunxi_lcdc_pll_set()
623 setbits_le32(&ccm->lcd0_ch1_clk_cfg, in sunxi_lcdc_pll_set()
640 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcdc_init()
642 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST); in sunxi_lcdc_init()
646 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_lcdc_init()
649 setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS); in sunxi_lcdc_init()
651 setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST); in sunxi_lcdc_init()
693 gpio_direction_output(reset_pin, 1); /* De-assert reset */ in sunxi_lcdc_panel_enable()
728 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
730 timing->hactive.typ = mode->xres; in sunxi_ctfb_mode_to_display_timing()
731 timing->hfront_porch.typ = mode->right_margin; in sunxi_ctfb_mode_to_display_timing()
732 timing->hback_porch.typ = mode->left_margin; in sunxi_ctfb_mode_to_display_timing()
733 timing->hsync_len.typ = mode->hsync_len; in sunxi_ctfb_mode_to_display_timing()
735 timing->vactive.typ = mode->yres; in sunxi_ctfb_mode_to_display_timing()
736 timing->vfront_porch.typ = mode->lower_margin; in sunxi_ctfb_mode_to_display_timing()
737 timing->vback_porch.typ = mode->upper_margin; in sunxi_ctfb_mode_to_display_timing()
738 timing->vsync_len.typ = mode->vsync_len; in sunxi_ctfb_mode_to_display_timing()
740 if (mode->sync & FB_SYNC_HOR_HIGH_ACT) in sunxi_ctfb_mode_to_display_timing()
741 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; in sunxi_ctfb_mode_to_display_timing()
743 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; in sunxi_ctfb_mode_to_display_timing()
744 if (mode->sync & FB_SYNC_VERT_HIGH_ACT) in sunxi_ctfb_mode_to_display_timing()
745 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; in sunxi_ctfb_mode_to_display_timing()
747 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; in sunxi_ctfb_mode_to_display_timing()
748 if (mode->vmode == FB_VMODE_INTERLACED) in sunxi_ctfb_mode_to_display_timing()
749 timing->flags |= DISPLAY_FLAGS_INTERLACED; in sunxi_ctfb_mode_to_display_timing()
776 sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
801 sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
824 if (mode->pixclock_khz <= 27000)
825 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
827 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
829 if (mode->xres * 100 / mode->yres < 156)
837 avi_info_frame[3] = 0x100 - checksum;
840 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
842 writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
843 writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
846 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
848 writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
849 writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
851 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
862 writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
868 writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
871 writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
872 writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
873 writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
874 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
875 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
878 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
881 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
884 writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
885 &hdmi->video_size);
887 x = mode->hsync_len + mode->left_margin;
888 y = mode->vsync_len + mode->upper_margin;
889 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
891 x = mode->right_margin;
892 y = mode->lower_margin;
893 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
895 x = mode->hsync_len;
896 y = mode->vsync_len;
897 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
899 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
900 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
902 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
903 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
912 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
927 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
929 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
963 /* On sun6i the drc must be clocked even when in pass-through mode */
965 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
967 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
968 clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
1006 if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
1010 if (cfg.reset_pin == -1) {
1121 case sunxi_monitor_composite_pal: return "composite-pal";
1122 case sunxi_monitor_composite_ntsc: return "composite-ntsc";
1123 case sunxi_monitor_composite_pal_m: return "composite-pal-m";
1124 case sunxi_monitor_composite_pal_nc: return "composite-pal-nc";
1131 return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
1205 overscan_x = video_get_option_int(options, "overscan_x", -1);
1206 overscan_y = video_get_option_int(options, "overscan_y", -1);
1284 if (overscan_x == -1)
1286 if (overscan_y == -1)
1290 (mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
1291 overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
1305 mode->xres, mode->yres,
1306 (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
1310 gd->fb_base = gd->bd->bi_dram[0].start +
1311 gd->bd->bi_dram[0].size - sunxi_display.fb_size;
1314 fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
1315 sunxi_display.fb_addr = gd->fb_base;
1317 fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
1319 memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
1320 flush_cache(gd->fb_base, sunxi_display.fb_size);
1328 graphic_device->frameAdrs = sunxi_display.fb_addr;
1329 graphic_device->gdfIndex = GDF_32BIT_X888RGB;
1330 graphic_device->gdfBytesPP = 4;
1331 graphic_device->winSizeX = mode->xres - 2 * overscan_x;
1332 graphic_device->winSizeY = mode->yres - 2 * overscan_y;
1333 graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
1350 #define PIPELINE_PREFIX "de_fe0-"
1360 pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi";
1363 pipeline = PIPELINE_PREFIX "de_be0-lcd0";
1367 pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
1369 pipeline = PIPELINE_PREFIX "de_be0-lcd0";
1376 pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
1381 offset = fdt_node_offset_by_compatible(blob, -1,
1382 "allwinner,simple-framebuffer");
1389 "allwinner,simple-framebuffer");
1402 start = gd->bd->bi_dram[0].start;
1403 size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
1411 graphic_device->winSizeX, graphic_device->winSizeY,
1412 graphic_device->plnSizeX, "x8r8g8b8");