Lines Matching +full:0 +full:xf004
16 #define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
20 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
21 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
23 #define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
24 #define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
25 #define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc)
26 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)
27 #define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
28 #define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108)
29 #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c)
30 #define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110)
31 #define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114)
32 #define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118)
33 #define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c)
34 #define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120)
35 #define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124)
36 #define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128)
37 #define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c)
38 #define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130)
39 #define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134)
40 #define MVEBU_LCD_SPU_COLORKEY_V (MVEBU_LCD_BASE + 0x0138)
41 #define MVEBU_LCD_CFG_RDREG4F (MVEBU_LCD_BASE + 0x013c)
42 #define MVEBU_LCD_SPU_SPI_RXDATA (MVEBU_LCD_BASE + 0x0140)
43 #define MVEBU_LCD_SPU_ISA_RXDATA (MVEBU_LCD_BASE + 0x0144)
44 #define MVEBU_LCD_SPU_DBG_ISA (MVEBU_LCD_BASE + 0x0148)
46 #define MVEBU_LCD_SPU_HWC_RDDAT (MVEBU_LCD_BASE + 0x0158)
47 #define MVEBU_LCD_SPU_GAMMA_RDDAT (MVEBU_LCD_BASE + 0x015c)
48 #define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160)
49 #define MVEBU_LCD_SPU_IOPAD_IN (MVEBU_LCD_BASE + 0x0178)
50 #define MVEBU_LCD_FRAME_COUNT (MVEBU_LCD_BASE + 0x017c)
51 #define MVEBU_LCD_SPU_DMA_CTRL0 (MVEBU_LCD_BASE + 0x0190)
52 #define MVEBU_LCD_SPU_DMA_CTRL1 (MVEBU_LCD_BASE + 0x0194)
53 #define MVEBU_LCD_SPU_SRAM_CTRL (MVEBU_LCD_BASE + 0x0198)
54 #define MVEBU_LCD_SPU_SRAM_WRDAT (MVEBU_LCD_BASE + 0x019c)
55 #define MVEBU_LCD_SPU_SRAM_PARA0 (MVEBU_LCD_BASE + 0x01a0)
56 #define MVEBU_LCD_SPU_SRAM_PARA1 (MVEBU_LCD_BASE + 0x01a4)
57 #define MVEBU_LCD_CFG_SCLK_DIV (MVEBU_LCD_BASE + 0x01a8)
58 #define MVEBU_LCD_SPU_CONTRAST (MVEBU_LCD_BASE + 0x01ac)
59 #define MVEBU_LCD_SPU_SATURATION (MVEBU_LCD_BASE + 0x01b0)
60 #define MVEBU_LCD_SPU_CBSH_HUE (MVEBU_LCD_BASE + 0x01b4)
61 #define MVEBU_LCD_SPU_DUMB_CTRL (MVEBU_LCD_BASE + 0x01b8)
62 #define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc)
63 #define MVEBU_LCD_SPU_IRQ_ENA_2 (MVEBU_LCD_BASE + 0x01d8)
64 #define MVEBU_LCD_SPU_IRQ_ISR_2 (MVEBU_LCD_BASE + 0x01dc)
65 #define MVEBU_LCD_SPU_IRQ_ENA (MVEBU_LCD_BASE + 0x01c0)
66 #define MVEBU_LCD_SPU_IRQ_ISR (MVEBU_LCD_BASE + 0x01c4)
67 #define MVEBU_LCD_ADLL_CTRL (MVEBU_LCD_BASE + 0x01c8)
68 #define MVEBU_LCD_CLK_DIS (MVEBU_LCD_BASE + 0x01cc)
69 #define MVEBU_LCD_VGA_HVSYNC_DELAY (MVEBU_LCD_BASE + 0x01d4)
70 #define MVEBU_LCD_CLK_CFG_0 (MVEBU_LCD_BASE + 0xf0a0)
71 #define MVEBU_LCD_CLK_CFG_1 (MVEBU_LCD_BASE + 0xf0a4)
72 #define MVEBU_LCD_LVDS_CLK_CFG (MVEBU_LCD_BASE + 0xf0ac)
74 #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
84 /* Disable windows, set size/base/remap to 0 */ in mvebu_lcd_conf_mbus_registers()
85 for (i = 0; i < 6; i++) { in mvebu_lcd_conf_mbus_registers()
86 writel(0, MVEBU_LCD_WIN_CONTROL(i)); in mvebu_lcd_conf_mbus_registers()
87 writel(0, MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
88 writel(0, MVEBU_LCD_WIN_REMAP(i)); in mvebu_lcd_conf_mbus_registers()
92 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
94 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()
98 writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
115 * wr 0 182F0 FFE00000 in mvebu_lcd_register_init()
117 clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16); in mvebu_lcd_register_init()
123 * See also the Window 0 settings! in mvebu_lcd_register_init()
130 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting) in mvebu_lcd_register_init()
132 * (here 16=0x10 for 1kHz) in mvebu_lcd_register_init()
134 * 240*2 (for RGB1555)=480=0x1E0 in mvebu_lcd_register_init()
136 writel(0x80100000 + 2 * x, MVEBU_LCD_CFG_GRA_PITCH); in mvebu_lcd_register_init()
143 writel(0x00000000, MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN); in mvebu_lcd_register_init()
147 * Bits 31-16: Vertical size of graphical overlay 320=0x140 in mvebu_lcd_register_init()
148 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 in mvebu_lcd_register_init()
155 * Bits 31-16: Vertical size of graphical overlay 320=0x140 in mvebu_lcd_register_init()
156 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 in mvebu_lcd_register_init()
163 * Bits 31-16: Vertical position of HW Cursor 320=0x140 in mvebu_lcd_register_init()
164 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0 in mvebu_lcd_register_init()
173 writel(0x00000000, MVEBU_LCD_SPU_HWC_HPXL_VLN); in mvebu_lcd_register_init()
182 * SUM = 325 = 0x0145 in mvebu_lcd_register_init()
188 * SUM = 287 = 0x011F in mvebu_lcd_register_init()
199 * Bits 31-16: Screen active vertical lines 320=0x140 in mvebu_lcd_register_init()
200 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0 in mvebu_lcd_register_init()
206 * Bits 31-16: Screen horizontal backporch 44=0x2c in mvebu_lcd_register_init()
207 * Bits 15-00: Screen horizontal frontporch 2=0x02 in mvebu_lcd_register_init()
215 * Bits 31-16: Screen vertical backporch 2=0x02 in mvebu_lcd_register_init()
216 * Bits 15-00: Screen vertical frontporch 2=0x02 in mvebu_lcd_register_init()
224 * This should be black = 0 in mvebu_lcd_register_init()
227 writel(0x00FF00FF, MVEBU_LCD_SPU_BLANKCOLOR); in mvebu_lcd_register_init()
230 * Registers in the range of 0x0128 to 0x012C are colors for the cursor in mvebu_lcd_register_init()
231 * Registers in the range of 0x0130 to 0x0138 are colors for video in mvebu_lcd_register_init()
240 * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved in mvebu_lcd_register_init()
241 * Bit 8: FIFO watermark for DMA: 0=disable in mvebu_lcd_register_init()
242 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80 in mvebu_lcd_register_init()
244 writel(0x00000780, MVEBU_LCD_CFG_RDREG4F); in mvebu_lcd_register_init()
247 * Set the LCD_SPU_DMACTRL 0 Register in mvebu_lcd_register_init()
249 * Bit 30: Gamma correction enable, 0=disable in mvebu_lcd_register_init()
250 * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable in mvebu_lcd_register_init()
251 * Bit 28: Color palette enable, 0=disable in mvebu_lcd_register_init()
255 * Bit 24: HW Cursor enabled, 0=disable in mvebu_lcd_register_init()
256 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555 in mvebu_lcd_register_init()
257 * Bits 19-16: Video Memory Color Format: 0x1=RGB1555 in mvebu_lcd_register_init()
258 * Bit 15: Memory Toggle between frame 0 and 1: 0=disable in mvebu_lcd_register_init()
259 * Bit 14: Graphics horizontal scaling enable: 0=disable in mvebu_lcd_register_init()
260 * Bit 13: Graphics test mode: 0=disable in mvebu_lcd_register_init()
261 * Bit 12: Graphics SWAP R and B: 0=disable in mvebu_lcd_register_init()
262 * Bit 11: Graphics SWAP U and V: 0=disable in mvebu_lcd_register_init()
263 * Bit 10: Graphics SWAP Y and U/V: 0=disable in mvebu_lcd_register_init()
264 * Bit 09: Graphic YUV to RGB Conversion: 0=disable in mvebu_lcd_register_init()
266 * Bit 07: Memory Toggle: 0=disable in mvebu_lcd_register_init()
267 * Bit 06: Video horizontal scaling enable: 0=disable in mvebu_lcd_register_init()
268 * Bit 05: Video test mode: 0=disable in mvebu_lcd_register_init()
269 * Bit 04: Video SWAP R and B: 0=disable in mvebu_lcd_register_init()
270 * Bit 03: Video SWAP U and V: 0=disable in mvebu_lcd_register_init()
271 * Bit 02: Video SWAP Y and U/V: 0=disable in mvebu_lcd_register_init()
272 * Bit 01: Video YUV to RGB Conversion: 0=disable in mvebu_lcd_register_init()
273 * Bit 00: Video Transfer: 0=disable in mvebu_lcd_register_init()
275 writel(0x88111100, MVEBU_LCD_SPU_DMA_CTRL0); in mvebu_lcd_register_init()
279 * Bit 31: Manual DMA Trigger = 0 in mvebu_lcd_register_init()
280 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC in mvebu_lcd_register_init()
281 * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge in mvebu_lcd_register_init()
282 * Bits 26-24: Color Key Mode: 0=disable in mvebu_lcd_register_init()
283 * Bit 23: Fill low bits: 0=fill with zeroes in mvebu_lcd_register_init()
285 * Bit 21: Gated Clock: 0=disable in mvebu_lcd_register_init()
286 * Bit 20: Power Save enable: 0=disable in mvebu_lcd_register_init()
288 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha. in mvebu_lcd_register_init()
289 * Bits 15-08: Configure Alpha: 0x00. in mvebu_lcd_register_init()
292 writel(0x20010000, MVEBU_LCD_SPU_DMA_CTRL1); in mvebu_lcd_register_init()
297 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2 in mvebu_lcd_register_init()
298 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb, in mvebu_lcd_register_init()
301 writel(0x0000C000, MVEBU_LCD_SPU_SRAM_CTRL); in mvebu_lcd_register_init()
308 writel(0x00000000, MVEBU_LCD_SPU_SRAM_PARA1); in mvebu_lcd_register_init()
315 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0 in mvebu_lcd_register_init()
316 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0 in mvebu_lcd_register_init()
318 writel(0x00000000, MVEBU_LCD_SPU_CONTRAST); in mvebu_lcd_register_init()
325 writel(0x10001000, MVEBU_LCD_SPU_SATURATION); in mvebu_lcd_register_init()
332 writel(0x00000000, MVEBU_LCD_SPU_CBSH_HUE); in mvebu_lcd_register_init()
348 * Bit 0: Enable LCD Panel: 1=Enable in mvebu_lcd_register_init()
352 writel(0x6000080F, MVEBU_LCD_SPU_DUMB_CTRL); in mvebu_lcd_register_init()
357 * Bits 19-18: Vertical Interpolation: 0=Disable in mvebu_lcd_register_init()
359 * Bit 15: Graphics Vertical Mirror enable: 0=disable in mvebu_lcd_register_init()
361 * Bit 13: Video Vertical Mirror enable: 0=disable in mvebu_lcd_register_init()
363 * Bit 11: Command Vertical Mirror enable: 0=disable in mvebu_lcd_register_init()
365 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used) in mvebu_lcd_register_init()
366 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary, in mvebu_lcd_register_init()
368 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ?? in mvebu_lcd_register_init()
370 writel(0x000000C0, MVEBU_LCD_SPU_IOPAD_CONTROL); in mvebu_lcd_register_init()
375 writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA_2); in mvebu_lcd_register_init()
380 writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA); in mvebu_lcd_register_init()
384 * Bits 31-29: 0x0 = Fastest Delay Line (default) in mvebu_lcd_register_init()
385 * 0x3 = Slowest Delay Line (default) in mvebu_lcd_register_init()
393 * Bits 19-16: Calibration Threshold voltage, default= 0x2 in mvebu_lcd_register_init()
395 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16 in mvebu_lcd_register_init()
397 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z in mvebu_lcd_register_init()
400 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay in mvebu_lcd_register_init()
403 writel(0x00000000, MVEBU_LCD_ADLL_CTRL); in mvebu_lcd_register_init()
409 writel(0x00000018, MVEBU_LCD_CLK_DIS); in mvebu_lcd_register_init()
415 writel(0x00000000, MVEBU_LCD_VGA_HVSYNC_DELAY); in mvebu_lcd_register_init()
427 writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1); in mvebu_lcd_register_init()
430 * Powerdown, see "LCD Clock Configuration 0 Register" below in mvebu_lcd_register_init()
432 writel(0x94000174, MVEBU_LCD_CLK_CFG_0); in mvebu_lcd_register_init()
436 * This is set fix to 0x40000001 for the LVDS output: in mvebu_lcd_register_init()
437 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0 in mvebu_lcd_register_init()
438 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001 in mvebu_lcd_register_init()
441 writel(0x80000001, MVEBU_LCD_CFG_SCLK_DIV); in mvebu_lcd_register_init()
444 * Set the LCD Clock Configuration 0 Register: in mvebu_lcd_register_init()
445 * Bit 31: Powerdown: 0=Power up in mvebu_lcd_register_init()
448 * K=16 => 0x5 in mvebu_lcd_register_init()
450 * M=1 => 0x0 in mvebu_lcd_register_init()
451 * Bits 16-13: VCO band: 0x1 for 700-920MHz in mvebu_lcd_register_init()
453 * N=28=0x1C => 0x1B in mvebu_lcd_register_init()
454 * Bits 03-00: R1_CTRL (for N=28 => 0x4) in mvebu_lcd_register_init()
456 writel(0x940021B4, MVEBU_LCD_CLK_CFG_0); in mvebu_lcd_register_init()
462 * Bit 17: Clock Output Enable: 0=disable, 1=enable in mvebu_lcd_register_init()
463 * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External in mvebu_lcd_register_init()
469 writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1); in mvebu_lcd_register_init()
476 * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7 in mvebu_lcd_register_init()
478 * Bit 01: 24bbp Option: 0=Option_1,1=Option2 in mvebu_lcd_register_init()
479 * Bit 00: 1=24bbp Panel: 0=18bpp Panel in mvebu_lcd_register_init()
480 * Note: Bits 0 and must be verified with the help of the in mvebu_lcd_register_init()
483 writel(0xC0000201, MVEBU_LCD_LVDS_CLK_CFG); in mvebu_lcd_register_init()
486 * Power up PLL (Clock Config 0) in mvebu_lcd_register_init()
488 writel(0x140021B4, MVEBU_LCD_CLK_CFG_0); in mvebu_lcd_register_init()
496 writel(0x8FF60007, MVEBU_LCD_CLK_CFG_1); in mvebu_lcd_register_init()
498 return 0; in mvebu_lcd_register_init()
523 pGD->winSizeX = val & 0x0000ffff; in video_hw_init()
528 debug("LCD: buffer at 0x%08x resolution %dx%d\n", pGD->frameAdrs, in video_hw_init()