Lines Matching +full:triple +full:- +full:channel
2 * Porting to u-boot:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/imx-regs.h>
68 /* disable DMFC-IC channel*/ in ipu_dmfc_init()
77 /* 1 - segment 0~3; in ipu_dmfc_init()
78 * 5B - segement 4, 5; in ipu_dmfc_init()
79 * 5F - segement 6, 7; in ipu_dmfc_init()
91 /* 1 - segment 0, 1; in ipu_dmfc_init()
92 * 5B - segement 2~5; in ipu_dmfc_init()
93 * 5F - segement 6,7; in ipu_dmfc_init()
105 /* 5B - segement 0~3; in ipu_dmfc_init()
106 * 5F - segement 4~7; in ipu_dmfc_init()
109 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n"); in ipu_dmfc_init()
118 /* 1 - segment 0, 1; in ipu_dmfc_init()
119 * 5B - segement 4, 5; in ipu_dmfc_init()
120 * 5F - segement 6, 7; in ipu_dmfc_init()
233 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); in ipu_di_sync_config()
234 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); in ipu_di_sync_config()
291 * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
292 * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
302 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
303 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
304 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
418 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, in ipu_dp_init() argument
426 if (channel == MEM_FG_SYNC) { in ipu_dp_init()
429 } else if (channel == MEM_BG_SYNC) { in ipu_dp_init()
432 } else if (channel == MEM_BG_ASYNC0) { in ipu_dp_init()
436 return -EINVAL; in ipu_dp_init()
505 void ipu_dp_uninit(ipu_channel_t channel) in ipu_dp_uninit() argument
510 if (channel == MEM_FG_SYNC) { in ipu_dp_uninit()
513 } else if (channel == MEM_BG_SYNC) { in ipu_dp_uninit()
516 } else if (channel == MEM_BG_ASYNC0) { in ipu_dp_uninit()
608 void ipu_dp_dc_enable(ipu_channel_t channel) in ipu_dp_dc_enable() argument
614 if (channel == MEM_DC_SYNC) in ipu_dp_dc_enable()
616 else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) in ipu_dp_dc_enable()
621 if (channel == MEM_FG_SYNC) { in ipu_dp_dc_enable()
622 /* Enable FG channel */ in ipu_dp_dc_enable()
633 /* Make sure other DC sync channel is not assigned same DI */ in ipu_dp_dc_enable()
634 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
638 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
650 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) in ipu_dp_dc_disable() argument
660 if (channel == MEM_DC_SYNC) { in ipu_dp_dc_disable()
663 } else if (channel == MEM_BG_SYNC) { in ipu_dp_dc_disable()
666 } else if (channel == MEM_FG_SYNC) { in ipu_dp_dc_disable()
667 /* Disable FG channel */ in ipu_dp_dc_disable()
684 * Wait for DC triple buffer to empty, in ipu_dp_dc_disable()
691 timeout -= 2; in ipu_dp_dc_disable()
699 timeout -= 2; in ipu_dp_dc_disable()
709 /* Swap DC channel 1 and 5 settings, and disable old dc chan */ in ipu_dp_dc_disable()
711 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_disable()
788 return -1; in ipu_pixfmt_to_map()
846 return -EINVAL; in ipu_init_sync_panel()
898 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); in ipu_init_sync_panel()
904 return -EINVAL; in ipu_init_sync_panel()
914 h_total / 2 - 1,/* run count */ in ipu_init_sync_panel()
931 h_total - 1, /* run count */ in ipu_init_sync_panel()
948 v_total * 2 - 1,/* run count */ in ipu_init_sync_panel()
965 v_total / 2 - 1,/* run count */ in ipu_init_sync_panel()
999 v_total - 1, /* run count */ in ipu_init_sync_panel()
1017 v_total / 2 - 1,/* run count */ in ipu_init_sync_panel()
1050 v_total - 1, /* run count */ in ipu_init_sync_panel()
1066 reg |= (3 - 1)<<29 | 0x00008000; in ipu_init_sync_panel()
1069 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); in ipu_init_sync_panel()
1077 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, in ipu_init_sync_panel()
1083 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, in ipu_init_sync_panel()
1089 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, in ipu_init_sync_panel()
1093 __raw_writel(v_total - 1, DI_SCR_CONF(disp)); in ipu_init_sync_panel()
1145 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | in ipu_init_sync_panel()
1164 * parameter of IPUv3 DP channel.
1166 * @param channel IPUv3 DP channel
1175 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, in ipu_disp_set_global_alpha() argument
1182 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || in ipu_disp_set_global_alpha()
1183 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || in ipu_disp_set_global_alpha()
1184 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) in ipu_disp_set_global_alpha()
1185 return -EINVAL; in ipu_disp_set_global_alpha()
1187 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || in ipu_disp_set_global_alpha()
1188 channel == MEM_BG_ASYNC1) in ipu_disp_set_global_alpha()
1228 * @param channel Input parameter for the logical channel ID.
1232 * @param colorKey 24-bit RGB color for transparent color key.
1236 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, in ipu_disp_set_color_key() argument
1243 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || in ipu_disp_set_color_key()
1244 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || in ipu_disp_set_color_key()
1245 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) in ipu_disp_set_color_key()
1246 return -EINVAL; in ipu_disp_set_color_key()