23 #define	dcu_write32	out_le32  macro
26 #define	dcu_write32	out_be32  macro
230 		dcu_write32(&regs->ctrldescl[i][0], 0);  in reset_total_layers()
231 		dcu_write32(&regs->ctrldescl[i][1], 0);  in reset_total_layers()
232 		dcu_write32(&regs->ctrldescl[i][2], 0);  in reset_total_layers()
233 		dcu_write32(&regs->ctrldescl[i][3], 0);  in reset_total_layers()
234 		dcu_write32(&regs->ctrldescl[i][4], 0);  in reset_total_layers()
235 		dcu_write32(&regs->ctrldescl[i][5], 0);  in reset_total_layers()
236 		dcu_write32(&regs->ctrldescl[i][6], 0);  in reset_total_layers()
237 		dcu_write32(&regs->ctrldescl[i][7], 0);  in reset_total_layers()
238 		dcu_write32(&regs->ctrldescl[i][8], 0);  in reset_total_layers()
239 		dcu_write32(&regs->ctrldescl[i][9], 0);  in reset_total_layers()
240 		dcu_write32(&regs->ctrldescl[i][10], 0);  in reset_total_layers()
249 	dcu_write32(&regs->ctrldescl[index][0],  in layer_ctrldesc_init()
253 	dcu_write32(&regs->ctrldescl[index][1],  in layer_ctrldesc_init()
257 	dcu_write32(&regs->ctrldescl[index][2], (unsigned int)info.screen_base);  in layer_ctrldesc_init()
273 	dcu_write32(&regs->ctrldescl[index][3],  in layer_ctrldesc_init()
279 	dcu_write32(&regs->ctrldescl[index][4],  in layer_ctrldesc_init()
283 	dcu_write32(&regs->ctrldescl[index][5],  in layer_ctrldesc_init()
288 	dcu_write32(&regs->ctrldescl[index][6],  in layer_ctrldesc_init()
292 	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));  in layer_ctrldesc_init()
293 	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));  in layer_ctrldesc_init()
321 	dcu_write32(&regs->disp_size,  in fsl_dcu_init()
325 	dcu_write32(&regs->hsyn_para,  in fsl_dcu_init()
330 	dcu_write32(&regs->vsyn_para,  in fsl_dcu_init()
335 	dcu_write32(&regs->synpol,  in fsl_dcu_init()
341 	dcu_write32(&regs->bgnd,  in fsl_dcu_init()
344 	dcu_write32(&regs->mode,  in fsl_dcu_init()
348 	dcu_write32(&regs->threshold,  in fsl_dcu_init()
354 	dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);  in fsl_dcu_init()
359 	dcu_write32(&regs->div_ratio, (div - 1));  in fsl_dcu_init()
361 	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);  in fsl_dcu_init()