Lines Matching refs:cfg
106 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
109 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
113 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
117 writel(cfg, ®->dualrgb); in exynos_fimd_set_dualrgb()
124 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
127 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
129 writel(cfg, ®->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
136 unsigned int cfg = 0; in exynos_fimd_set_par() local
139 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_set_par()
142 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
148 cfg |= EXYNOS_WINCON_DATAPATH_DMA; in exynos_fimd_set_par()
150 cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; in exynos_fimd_set_par()
153 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; in exynos_fimd_set_par()
157 cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; in exynos_fimd_set_par()
160 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; in exynos_fimd_set_par()
164 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_set_par()
168 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); in exynos_fimd_set_par()
169 writel(cfg, (unsigned int)®->vidosd0a + in exynos_fimd_set_par()
172 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | in exynos_fimd_set_par()
177 writel(cfg, (unsigned int)®->vidosd0b + in exynos_fimd_set_par()
181 cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row); in exynos_fimd_set_par()
182 writel(cfg, (unsigned int)®->vidosd0c + in exynos_fimd_set_par()
206 unsigned int cfg = 0, div = 0, remainder, remainder_div; in exynos_fimd_set_clock() local
229 cfg = readl(®->vidcon0); in exynos_fimd_set_clock()
230 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | in exynos_fimd_set_clock()
233 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | in exynos_fimd_set_clock()
253 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); in exynos_fimd_set_clock()
254 writel(cfg, ®->vidcon0); in exynos_fimd_set_clock()
260 unsigned int cfg = 0; in exynos_set_trigger() local
262 cfg = readl(®->trigcon); in exynos_set_trigger()
264 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); in exynos_set_trigger()
266 writel(cfg, ®->trigcon); in exynos_set_trigger()
272 unsigned int cfg = 0; in exynos_is_i80_frame_done() local
275 cfg = readl(®->trigcon); in exynos_is_i80_frame_done()
278 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == in exynos_is_i80_frame_done()
287 unsigned int cfg = 0; in exynos_fimd_lcd_on() local
290 cfg = readl(®->vidcon0); in exynos_fimd_lcd_on()
291 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); in exynos_fimd_lcd_on()
292 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_on()
299 unsigned int cfg = 0; in exynos_fimd_window_on() local
302 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_on()
304 cfg |= EXYNOS_WINCON_ENWIN_ENABLE; in exynos_fimd_window_on()
305 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_on()
308 cfg = readl(®->winshmap); in exynos_fimd_window_on()
309 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); in exynos_fimd_window_on()
310 writel(cfg, ®->winshmap); in exynos_fimd_window_on()
316 unsigned int cfg = 0; in exynos_fimd_lcd_off() local
318 cfg = readl(®->vidcon0); in exynos_fimd_lcd_off()
319 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); in exynos_fimd_lcd_off()
320 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_off()
326 unsigned int cfg = 0; in exynos_fimd_window_off() local
328 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_off()
330 cfg &= EXYNOS_WINCON_ENWIN_DISABLE; in exynos_fimd_window_off()
331 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_off()
334 cfg = readl(®->winshmap); in exynos_fimd_window_off()
335 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); in exynos_fimd_window_off()
336 writel(cfg, ®->winshmap); in exynos_fimd_window_off()
382 unsigned int cfg = 0, rgb_mode; in exynos_fimd_lcd_init() local
395 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; in exynos_fimd_lcd_init()
396 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
398 cfg = readl(®->vidcon2); in exynos_fimd_lcd_init()
399 cfg &= ~(EXYNOS_VIDCON2_WB_MASK | in exynos_fimd_lcd_init()
402 cfg |= EXYNOS_VIDCON2_WB_DISABLE; in exynos_fimd_lcd_init()
403 writel(cfg, ®->vidcon2); in exynos_fimd_lcd_init()
406 cfg = 0; in exynos_fimd_lcd_init()
408 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; in exynos_fimd_lcd_init()
410 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; in exynos_fimd_lcd_init()
412 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; in exynos_fimd_lcd_init()
414 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; in exynos_fimd_lcd_init()
416 writel(cfg, (unsigned int)®->vidcon1 + offset); in exynos_fimd_lcd_init()
419 cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1); in exynos_fimd_lcd_init()
420 cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1); in exynos_fimd_lcd_init()
421 cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1); in exynos_fimd_lcd_init()
422 writel(cfg, (unsigned int)®->vidtcon0 + offset); in exynos_fimd_lcd_init()
424 cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1); in exynos_fimd_lcd_init()
425 cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1); in exynos_fimd_lcd_init()
426 cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1); in exynos_fimd_lcd_init()
428 writel(cfg, (unsigned int)®->vidtcon1 + offset); in exynos_fimd_lcd_init()
431 cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) | in exynos_fimd_lcd_init()
436 writel(cfg, (unsigned int)®->vidtcon2 + offset); in exynos_fimd_lcd_init()
440 cfg = readl(®->vidcon0); in exynos_fimd_lcd_init()
441 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; in exynos_fimd_lcd_init()
442 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); in exynos_fimd_lcd_init()
443 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
452 cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col * in exynos_fimd_lcd_init()
459 writel(cfg, (unsigned int)®->vidw00add2 + in exynos_fimd_lcd_init()