Lines Matching +full:0 +full:x00a8
11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
21 #define RK3288_WIN0_CTRL0 0x0030
22 #define RK3288_WIN0_CTRL1 0x0034
23 #define RK3288_WIN0_COLOR_KEY 0x0038
24 #define RK3288_WIN0_VIR 0x003c
25 #define RK3288_WIN0_YRGB_MST 0x0040
26 #define RK3288_WIN0_CBR_MST 0x0044
27 #define RK3288_WIN0_ACT_INFO 0x0048
28 #define RK3288_WIN0_DSP_INFO 0x004c
29 #define RK3288_WIN0_DSP_ST 0x0050
30 #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
31 #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
32 #define RK3288_WIN0_SCL_OFFSET 0x005c
33 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
34 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
35 #define RK3288_WIN0_FADING_CTRL 0x0068
38 #define RK3288_WIN1_CTRL0 0x0070
39 #define RK3288_WIN1_CTRL1 0x0074
40 #define RK3288_WIN1_COLOR_KEY 0x0078
41 #define RK3288_WIN1_VIR 0x007c
42 #define RK3288_WIN1_YRGB_MST 0x0080
43 #define RK3288_WIN1_CBR_MST 0x0084
44 #define RK3288_WIN1_ACT_INFO 0x0088
45 #define RK3288_WIN1_DSP_INFO 0x008c
46 #define RK3288_WIN1_DSP_ST 0x0090
47 #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
48 #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
49 #define RK3288_WIN1_SCL_OFFSET 0x009c
50 #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
51 #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
52 #define RK3288_WIN1_FADING_CTRL 0x00a8
54 #define RK3288_WIN2_CTRL0 0x00b0
55 #define RK3288_WIN2_CTRL1 0x00b4
56 #define RK3288_WIN2_VIR0_1 0x00b8
57 #define RK3288_WIN2_VIR2_3 0x00bc
58 #define RK3288_WIN2_MST0 0x00c0
59 #define RK3288_WIN2_DSP_INFO0 0x00c4
60 #define RK3288_WIN2_DSP_ST0 0x00c8
61 #define RK3288_WIN2_COLOR_KEY 0x00cc
62 #define RK3288_WIN2_MST1 0x00d0
63 #define RK3288_WIN2_DSP_INFO1 0x00d4
64 #define RK3288_WIN2_DSP_ST1 0x00d8
65 #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
66 #define RK3288_WIN2_MST2 0x00e0
67 #define RK3288_WIN2_DSP_INFO2 0x00e4
68 #define RK3288_WIN2_DSP_ST2 0x00e8
69 #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
70 #define RK3288_WIN2_MST3 0x00f0
71 #define RK3288_WIN2_DSP_INFO3 0x00f4
72 #define RK3288_WIN2_DSP_ST3 0x00f8
73 #define RK3288_WIN2_FADING_CTRL 0x00fc
75 #define RK3288_WIN3_CTRL0 0x0100
76 #define RK3288_WIN3_CTRL1 0x0104
77 #define RK3288_WIN3_VIR0_1 0x0108
78 #define RK3288_WIN3_VIR2_3 0x010c
79 #define RK3288_WIN3_MST0 0x0110
80 #define RK3288_WIN3_DSP_INFO0 0x0114
81 #define RK3288_WIN3_DSP_ST0 0x0118
82 #define RK3288_WIN3_COLOR_KEY 0x011c
83 #define RK3288_WIN3_MST1 0x0120
84 #define RK3288_WIN3_DSP_INFO1 0x0124
85 #define RK3288_WIN3_DSP_ST1 0x0128
86 #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
87 #define RK3288_WIN3_MST2 0x0130
88 #define RK3288_WIN3_DSP_INFO2 0x0134
89 #define RK3288_WIN3_DSP_ST2 0x0138
90 #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
91 #define RK3288_WIN3_MST3 0x0140
92 #define RK3288_WIN3_DSP_INFO3 0x0144
93 #define RK3288_WIN3_DSP_ST3 0x0148
94 #define RK3288_WIN3_FADING_CTRL 0x014c
96 #define RK3288_HWC_CTRL0 0x0150
97 #define RK3288_HWC_CTRL1 0x0154
98 #define RK3288_HWC_MST 0x0158
99 #define RK3288_HWC_DSP_ST 0x015c
100 #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
101 #define RK3288_HWC_DST_ALPHA_CTRL 0x0164
102 #define RK3288_HWC_FADING_CTRL 0x0168
104 #define RK3288_POST_DSP_HACT_INFO 0x0170
105 #define RK3288_POST_DSP_VACT_INFO 0x0174
106 #define RK3288_POST_SCL_FACTOR_YRGB 0x0178
107 #define RK3288_POST_SCL_CTRL 0x0180
108 #define RK3288_POST_DSP_VACT_INFO_F1 0x0184
109 #define RK3288_DSP_HTOTAL_HS_END 0x0188
110 #define RK3288_DSP_HACT_ST_END 0x018c
111 #define RK3288_DSP_VTOTAL_VS_END 0x0190
112 #define RK3288_DSP_VACT_ST_END 0x0194
113 #define RK3288_DSP_VS_ST_END_F1 0x0198
114 #define RK3288_DSP_VACT_ST_END_F1 0x019c
116 #define RK3288_BCSH_COLOR_BAR 0x01b0
117 #define RK3288_BCSH_BCS 0x01b4
118 #define RK3288_BCSH_H 0x01b8
119 #define RK3288_GRF_SOC_CON15 0x03a4
121 #define RK3288_MCU_BYPASS_WPORT 0x2200
125 #define RK3368_REG_CFG_DONE 0x0000
126 #define RK3368_VERSION_INFO 0x0004
127 #define RK3368_SYS_CTRL 0x0008
128 #define RK3368_SYS_CTRL1 0x000c
129 #define RK3368_DSP_CTRL0 0x0010
130 #define RK3368_DSP_CTRL1 0x0014
131 #define RK3368_DSP_BG 0x0018
132 #define RK3368_MCU_CTRL 0x001c
133 #define RK3368_LINE_FLAG 0x0020
134 #define RK3368_INTR_EN 0x0024
135 #define RK3368_INTR_CLEAR 0x0028
136 #define RK3368_INTR_STATUS 0x002c
137 #define RK3368_WIN0_CTRL0 0x0030
138 #define RK3368_WIN0_CTRL1 0x0034
139 #define RK3368_WIN0_COLOR_KEY 0x0038
140 #define RK3368_WIN0_VIR 0x003c
141 #define RK3368_WIN0_YRGB_MST 0x0040
142 #define RK3368_WIN0_CBR_MST 0x0044
143 #define RK3368_WIN0_ACT_INFO 0x0048
144 #define RK3368_WIN0_DSP_INFO 0x004c
145 #define RK3368_WIN0_DSP_ST 0x0050
146 #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054
147 #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058
148 #define RK3368_WIN0_SCL_OFFSET 0x005c
149 #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060
150 #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064
151 #define RK3368_WIN0_FADING_CTRL 0x0068
152 #define RK3368_WIN0_CTRL2 0x006c
153 #define RK3368_WIN1_CTRL0 0x0070
154 #define RK3368_WIN1_CTRL1 0x0074
155 #define RK3368_WIN1_COLOR_KEY 0x0078
156 #define RK3368_WIN1_VIR 0x007c
157 #define RK3368_WIN1_YRGB_MST 0x0080
158 #define RK3368_WIN1_CBR_MST 0x0084
159 #define RK3368_WIN1_ACT_INFO 0x0088
160 #define RK3368_WIN1_DSP_INFO 0x008c
161 #define RK3368_WIN1_DSP_ST 0x0090
162 #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094
163 #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098
164 #define RK3368_WIN1_SCL_OFFSET 0x009c
165 #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0
166 #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4
167 #define RK3368_WIN1_FADING_CTRL 0x00a8
168 #define RK3368_WIN1_CTRL2 0x00ac
169 #define RK3368_WIN2_CTRL0 0x00b0
170 #define RK3368_WIN2_CTRL1 0x00b4
171 #define RK3368_WIN2_VIR0_1 0x00b8
172 #define RK3368_WIN2_VIR2_3 0x00bc
173 #define RK3368_WIN2_MST0 0x00c0
174 #define RK3368_WIN2_DSP_INFO0 0x00c4
175 #define RK3368_WIN2_DSP_ST0 0x00c8
176 #define RK3368_WIN2_COLOR_KEY 0x00cc
177 #define RK3368_WIN2_MST1 0x00d0
178 #define RK3368_WIN2_DSP_INFO1 0x00d4
179 #define RK3368_WIN2_DSP_ST1 0x00d8
180 #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc
181 #define RK3368_WIN2_MST2 0x00e0
182 #define RK3368_WIN2_DSP_INFO2 0x00e4
183 #define RK3368_WIN2_DSP_ST2 0x00e8
184 #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec
185 #define RK3368_WIN2_MST3 0x00f0
186 #define RK3368_WIN2_DSP_INFO3 0x00f4
187 #define RK3368_WIN2_DSP_ST3 0x00f8
188 #define RK3368_WIN2_FADING_CTRL 0x00fc
189 #define RK3368_WIN3_CTRL0 0x0100
190 #define RK3368_WIN3_CTRL1 0x0104
191 #define RK3368_WIN3_VIR0_1 0x0108
192 #define RK3368_WIN3_VIR2_3 0x010c
193 #define RK3368_WIN3_MST0 0x0110
194 #define RK3368_WIN3_DSP_INFO0 0x0114
195 #define RK3368_WIN3_DSP_ST0 0x0118
196 #define RK3368_WIN3_COLOR_KEY 0x011c
197 #define RK3368_WIN3_MST1 0x0120
198 #define RK3368_WIN3_DSP_INFO1 0x0124
199 #define RK3368_WIN3_DSP_ST1 0x0128
200 #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c
201 #define RK3368_WIN3_MST2 0x0130
202 #define RK3368_WIN3_DSP_INFO2 0x0134
203 #define RK3368_WIN3_DSP_ST2 0x0138
204 #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c
205 #define RK3368_WIN3_MST3 0x0140
206 #define RK3368_WIN3_DSP_INFO3 0x0144
207 #define RK3368_WIN3_DSP_ST3 0x0148
208 #define RK3368_WIN3_FADING_CTRL 0x014c
209 #define RK3368_HWC_CTRL0 0x0150
210 #define RK3368_HWC_CTRL1 0x0154
211 #define RK3368_HWC_MST 0x0158
212 #define RK3368_HWC_DSP_ST 0x015c
213 #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160
214 #define RK3368_HWC_DST_ALPHA_CTRL 0x0164
215 #define RK3368_HWC_FADING_CTRL 0x0168
216 #define RK3368_HWC_RESERVED1 0x016c
217 #define RK3368_POST_DSP_HACT_INFO 0x0170
218 #define RK3368_POST_DSP_VACT_INFO 0x0174
219 #define RK3368_POST_SCL_FACTOR_YRGB 0x0178
220 #define RK3368_POST_RESERVED 0x017c
221 #define RK3368_POST_SCL_CTRL 0x0180
222 #define RK3368_POST_DSP_VACT_INFO_F1 0x0184
223 #define RK3368_DSP_HTOTAL_HS_END 0x0188
224 #define RK3368_DSP_HACT_ST_END 0x018c
225 #define RK3368_DSP_VTOTAL_VS_END 0x0190
226 #define RK3368_DSP_VACT_ST_END 0x0194
227 #define RK3368_DSP_VS_ST_END_F1 0x0198
228 #define RK3368_DSP_VACT_ST_END_F1 0x019c
229 #define RK3368_PWM_CTRL 0x01a0
230 #define RK3368_PWM_PERIOD_HPR 0x01a4
231 #define RK3368_PWM_DUTY_LPR 0x01a8
232 #define RK3368_PWM_CNT 0x01ac
233 #define RK3368_BCSH_COLOR_BAR 0x01b0
234 #define RK3368_BCSH_BCS 0x01b4
235 #define RK3368_BCSH_H 0x01b8
236 #define RK3368_BCSH_CTRL 0x01bc
237 #define RK3368_CABC_CTRL0 0x01c0
238 #define RK3368_CABC_CTRL1 0x01c4
239 #define RK3368_CABC_CTRL2 0x01c8
240 #define RK3368_CABC_CTRL3 0x01cc
241 #define RK3368_CABC_GAUSS_LINE0_0 0x01d0
242 #define RK3368_CABC_GAUSS_LINE0_1 0x01d4
243 #define RK3368_CABC_GAUSS_LINE1_0 0x01d8
244 #define RK3368_CABC_GAUSS_LINE1_1 0x01dc
245 #define RK3368_CABC_GAUSS_LINE2_0 0x01e0
246 #define RK3368_CABC_GAUSS_LINE2_1 0x01e4
247 #define RK3368_FRC_LOWER01_0 0x01e8
248 #define RK3368_FRC_LOWER01_1 0x01ec
249 #define RK3368_FRC_LOWER10_0 0x01f0
250 #define RK3368_FRC_LOWER10_1 0x01f4
251 #define RK3368_FRC_LOWER11_0 0x01f8
252 #define RK3368_FRC_LOWER11_1 0x01fc
253 #define RK3368_IFBDC_CTRL 0x0200
254 #define RK3368_IFBDC_TILES_NUM 0x0204
255 #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208
256 #define RK3368_IFBDC_BASE_ADDR 0x020c
257 #define RK3368_IFBDC_MB_SIZE 0x0210
258 #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214
259 #define RK3368_IFBDC_VIR 0x0220
260 #define RK3368_IFBDC_DEBUG0 0x0230
261 #define RK3368_IFBDC_DEBUG1 0x0234
262 #define RK3368_LATENCY_CTRL0 0x0250
263 #define RK3368_RD_MAX_LATENCY_NUM0 0x0254
264 #define RK3368_RD_LATENCY_THR_NUM0 0x0258
265 #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c
266 #define RK3368_WIN0_DSP_BG 0x0260
267 #define RK3368_WIN1_DSP_BG 0x0264
268 #define RK3368_WIN2_DSP_BG 0x0268
269 #define RK3368_WIN3_DSP_BG 0x026c
270 #define RK3368_SCAN_LINE_NUM 0x0270
271 #define RK3368_CABC_DEBUG0 0x0274
272 #define RK3368_CABC_DEBUG1 0x0278
273 #define RK3368_CABC_DEBUG2 0x027c
274 #define RK3368_DBG_REG_000 0x0280
275 #define RK3368_DBG_REG_001 0x0284
276 #define RK3368_DBG_REG_002 0x0288
277 #define RK3368_DBG_REG_003 0x028c
278 #define RK3368_DBG_REG_004 0x0290
279 #define RK3368_DBG_REG_005 0x0294
280 #define RK3368_DBG_REG_006 0x0298
281 #define RK3368_DBG_REG_007 0x029c
282 #define RK3368_DBG_REG_008 0x02a0
283 #define RK3368_DBG_REG_016 0x02c0
284 #define RK3368_DBG_REG_017 0x02c4
285 #define RK3368_DBG_REG_018 0x02c8
286 #define RK3368_DBG_REG_019 0x02cc
287 #define RK3368_DBG_REG_020 0x02d0
288 #define RK3368_DBG_REG_021 0x02d4
289 #define RK3368_DBG_REG_022 0x02d8
290 #define RK3368_DBG_REG_023 0x02dc
291 #define RK3368_DBG_REG_028 0x02f0
292 #define RK3368_MMU_DTE_ADDR 0x0300
293 #define RK3368_MMU_STATUS 0x0304
294 #define RK3368_MMU_COMMAND 0x0308
295 #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c
296 #define RK3368_MMU_ZAP_ONE_LINE 0x0310
297 #define RK3368_MMU_INT_RAWSTAT 0x0314
298 #define RK3368_MMU_INT_CLEAR 0x0318
299 #define RK3368_MMU_INT_MASK 0x031c
300 #define RK3368_MMU_INT_STATUS 0x0320
301 #define RK3368_MMU_AUTO_GATING 0x0324
302 #define RK3368_WIN2_LUT_ADDR 0x0400
303 #define RK3368_WIN3_LUT_ADDR 0x0800
304 #define RK3368_HWC_LUT_ADDR 0x0c00
305 #define RK3368_GAMMA_LUT_ADDR 0x1000
306 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800
307 #define RK3368_MCU_BYPASS_WPORT 0x2200
308 #define RK3368_MCU_BYPASS_RPORT 0x2300
309 #define RK3368_GRF_SOC_CON6 0x0418
312 #define RK3366_REG_CFG_DONE 0x0000
313 #define RK3366_VERSION_INFO 0x0004
314 #define RK3366_SYS_CTRL 0x0008
315 #define RK3366_SYS_CTRL1 0x000c
316 #define RK3366_DSP_CTRL0 0x0010
317 #define RK3366_DSP_CTRL1 0x0014
318 #define RK3366_DSP_BG 0x0018
319 #define RK3366_MCU_CTRL 0x001c
320 #define RK3366_WB_CTRL0 0x0020
321 #define RK3366_WB_CTRL1 0x0024
322 #define RK3366_WB_YRGB_MST 0x0028
323 #define RK3366_WB_CBR_MST 0x002c
324 #define RK3366_WIN0_CTRL0 0x0030
325 #define RK3366_WIN0_CTRL1 0x0034
326 #define RK3366_WIN0_COLOR_KEY 0x0038
327 #define RK3366_WIN0_VIR 0x003c
328 #define RK3366_WIN0_YRGB_MST 0x0040
329 #define RK3366_WIN0_CBR_MST 0x0044
330 #define RK3366_WIN0_ACT_INFO 0x0048
331 #define RK3366_WIN0_DSP_INFO 0x004c
332 #define RK3366_WIN0_DSP_ST 0x0050
333 #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054
334 #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058
335 #define RK3366_WIN0_SCL_OFFSET 0x005c
336 #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060
337 #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064
338 #define RK3366_WIN0_FADING_CTRL 0x0068
339 #define RK3366_WIN0_CTRL2 0x006c
340 #define RK3366_WIN1_CTRL0 0x0070
341 #define RK3366_WIN1_CTRL1 0x0074
342 #define RK3366_WIN1_COLOR_KEY 0x0078
343 #define RK3366_WIN1_VIR 0x007c
344 #define RK3366_WIN1_YRGB_MST 0x0080
345 #define RK3366_WIN1_CBR_MST 0x0084
346 #define RK3366_WIN1_ACT_INFO 0x0088
347 #define RK3366_WIN1_DSP_INFO 0x008c
348 #define RK3366_WIN1_DSP_ST 0x0090
349 #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094
350 #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098
351 #define RK3366_WIN1_SCL_OFFSET 0x009c
352 #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0
353 #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4
354 #define RK3366_WIN1_FADING_CTRL 0x00a8
355 #define RK3366_WIN1_CTRL2 0x00ac
356 #define RK3366_WIN2_CTRL0 0x00b0
357 #define RK3366_WIN2_CTRL1 0x00b4
358 #define RK3366_WIN2_VIR0_1 0x00b8
359 #define RK3366_WIN2_VIR2_3 0x00bc
360 #define RK3366_WIN2_MST0 0x00c0
361 #define RK3366_WIN2_DSP_INFO0 0x00c4
362 #define RK3366_WIN2_DSP_ST0 0x00c8
363 #define RK3366_WIN2_COLOR_KEY 0x00cc
364 #define RK3366_WIN2_MST1 0x00d0
365 #define RK3366_WIN2_DSP_INFO1 0x00d4
366 #define RK3366_WIN2_DSP_ST1 0x00d8
367 #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc
368 #define RK3366_WIN2_MST2 0x00e0
369 #define RK3366_WIN2_DSP_INFO2 0x00e4
370 #define RK3366_WIN2_DSP_ST2 0x00e8
371 #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec
372 #define RK3366_WIN2_MST3 0x00f0
373 #define RK3366_WIN2_DSP_INFO3 0x00f4
374 #define RK3366_WIN2_DSP_ST3 0x00f8
375 #define RK3366_WIN2_FADING_CTRL 0x00fc
376 #define RK3366_WIN3_CTRL0 0x0100
377 #define RK3366_WIN3_CTRL1 0x0104
378 #define RK3366_WIN3_VIR0_1 0x0108
379 #define RK3366_WIN3_VIR2_3 0x010c
380 #define RK3366_WIN3_MST0 0x0110
381 #define RK3366_WIN3_DSP_INFO0 0x0114
382 #define RK3366_WIN3_DSP_ST0 0x0118
383 #define RK3366_WIN3_COLOR_KEY 0x011c
384 #define RK3366_WIN3_MST1 0x0120
385 #define RK3366_WIN3_DSP_INFO1 0x0124
386 #define RK3366_WIN3_DSP_ST1 0x0128
387 #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c
388 #define RK3366_WIN3_MST2 0x0130
389 #define RK3366_WIN3_DSP_INFO2 0x0134
390 #define RK3366_WIN3_DSP_ST2 0x0138
391 #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c
392 #define RK3366_WIN3_MST3 0x0140
393 #define RK3366_WIN3_DSP_INFO3 0x0144
394 #define RK3366_WIN3_DSP_ST3 0x0148
395 #define RK3366_WIN3_FADING_CTRL 0x014c
396 #define RK3366_HWC_CTRL0 0x0150
397 #define RK3366_HWC_CTRL1 0x0154
398 #define RK3366_HWC_MST 0x0158
399 #define RK3366_HWC_DSP_ST 0x015c
400 #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160
401 #define RK3366_HWC_DST_ALPHA_CTRL 0x0164
402 #define RK3366_HWC_FADING_CTRL 0x0168
403 #define RK3366_HWC_RESERVED1 0x016c
404 #define RK3366_POST_DSP_HACT_INFO 0x0170
405 #define RK3366_POST_DSP_VACT_INFO 0x0174
406 #define RK3366_POST_SCL_FACTOR_YRGB 0x0178
407 #define RK3366_POST_RESERVED 0x017c
408 #define RK3366_POST_SCL_CTRL 0x0180
409 #define RK3366_POST_DSP_VACT_INFO_F1 0x0184
410 #define RK3366_DSP_HTOTAL_HS_END 0x0188
411 #define RK3366_DSP_HACT_ST_END 0x018c
412 #define RK3366_DSP_VTOTAL_VS_END 0x0190
413 #define RK3366_DSP_VACT_ST_END 0x0194
414 #define RK3366_DSP_VS_ST_END_F1 0x0198
415 #define RK3366_DSP_VACT_ST_END_F1 0x019c
416 #define RK3366_PWM_CTRL 0x01a0
417 #define RK3366_PWM_PERIOD_HPR 0x01a4
418 #define RK3366_PWM_DUTY_LPR 0x01a8
419 #define RK3366_PWM_CNT 0x01ac
420 #define RK3366_BCSH_COLOR_BAR 0x01b0
421 #define RK3366_BCSH_BCS 0x01b4
422 #define RK3366_BCSH_H 0x01b8
423 #define RK3366_BCSH_CTRL 0x01bc
424 #define RK3366_CABC_CTRL0 0x01c0
425 #define RK3366_CABC_CTRL1 0x01c4
426 #define RK3366_CABC_CTRL2 0x01c8
427 #define RK3366_CABC_CTRL3 0x01cc
428 #define RK3366_CABC_GAUSS_LINE0_0 0x01d0
429 #define RK3366_CABC_GAUSS_LINE0_1 0x01d4
430 #define RK3366_CABC_GAUSS_LINE1_0 0x01d8
431 #define RK3366_CABC_GAUSS_LINE1_1 0x01dc
432 #define RK3366_CABC_GAUSS_LINE2_0 0x01e0
433 #define RK3366_CABC_GAUSS_LINE2_1 0x01e4
434 #define RK3366_FRC_LOWER01_0 0x01e8
435 #define RK3366_FRC_LOWER01_1 0x01ec
436 #define RK3366_FRC_LOWER10_0 0x01f0
437 #define RK3366_FRC_LOWER10_1 0x01f4
438 #define RK3366_FRC_LOWER11_0 0x01f8
439 #define RK3366_FRC_LOWER11_1 0x01fc
440 #define RK3366_INTR_EN0 0x0280
441 #define RK3366_INTR_CLEAR0 0x0284
442 #define RK3366_INTR_STATUS0 0x0288
443 #define RK3366_INTR_RAW_STATUS0 0x028c
444 #define RK3366_INTR_EN1 0x0290
445 #define RK3366_INTR_CLEAR1 0x0294
446 #define RK3366_INTR_STATUS1 0x0298
447 #define RK3366_INTR_RAW_STATUS1 0x029c
448 #define RK3366_LINE_FLAG 0x02a0
449 #define RK3366_VOP_STATUS 0x02a4
450 #define RK3366_BLANKING_VALUE 0x02a8
451 #define RK3366_WIN0_DSP_BG 0x02b0
452 #define RK3366_WIN1_DSP_BG 0x02b4
453 #define RK3366_WIN2_DSP_BG 0x02b8
454 #define RK3366_WIN3_DSP_BG 0x02bc
455 #define RK3366_WIN2_LUT_ADDR 0x0400
456 #define RK3366_WIN3_LUT_ADDR 0x0800
457 #define RK3366_HWC_LUT_ADDR 0x0c00
458 #define RK3366_GAMMA0_LUT_ADDR 0x1000
459 #define RK3366_GAMMA1_LUT_ADDR 0x1400
460 #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800
461 #define RK3366_MCU_BYPASS_WPORT 0x2200
462 #define RK3366_MCU_BYPASS_RPORT 0x2300
463 #define RK3366_MMU_DTE_ADDR 0x2400
464 #define RK3366_MMU_STATUS 0x2404
465 #define RK3366_MMU_COMMAND 0x2408
466 #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c
467 #define RK3366_MMU_ZAP_ONE_LINE 0x2410
468 #define RK3366_MMU_INT_RAWSTAT 0x2414
469 #define RK3366_MMU_INT_CLEAR 0x2418
470 #define RK3366_MMU_INT_MASK 0x241c
471 #define RK3366_MMU_INT_STATUS 0x2420
472 #define RK3366_MMU_AUTO_GATING 0x2424
475 #define RK3399_REG_CFG_DONE 0x0000
476 #define RK3399_VERSION_INFO 0x0004
477 #define RK3399_SYS_CTRL 0x0008
478 #define RK3399_SYS_CTRL1 0x000c
479 #define RK3399_DSP_CTRL0 0x0010
480 #define RK3399_DSP_CTRL1 0x0014
481 #define RK3399_DSP_BG 0x0018
482 #define RK3399_MCU_CTRL 0x001c
483 #define RK3399_WB_CTRL0 0x0020
484 #define RK3399_WB_CTRL1 0x0024
485 #define RK3399_WB_YRGB_MST 0x0028
486 #define RK3399_WB_CBR_MST 0x002c
487 #define RK3399_WIN0_CTRL0 0x0030
488 #define RK3399_WIN0_CTRL1 0x0034
489 #define RK3399_WIN0_COLOR_KEY 0x0038
490 #define RK3399_WIN0_VIR 0x003c
491 #define RK3399_WIN0_YRGB_MST 0x0040
492 #define RK3399_WIN0_CBR_MST 0x0044
493 #define RK3399_WIN0_ACT_INFO 0x0048
494 #define RK3399_WIN0_DSP_INFO 0x004c
495 #define RK3399_WIN0_DSP_ST 0x0050
496 #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054
497 #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058
498 #define RK3399_WIN0_SCL_OFFSET 0x005c
499 #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060
500 #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064
501 #define RK3399_WIN0_FADING_CTRL 0x0068
502 #define RK3399_WIN0_CTRL2 0x006c
503 #define RK3399_WIN1_CTRL0 0x0070
504 #define RK3399_WIN1_CTRL1 0x0074
505 #define RK3399_WIN1_COLOR_KEY 0x0078
506 #define RK3399_WIN1_VIR 0x007c
507 #define RK3399_WIN1_YRGB_MST 0x0080
508 #define RK3399_WIN1_CBR_MST 0x0084
509 #define RK3399_WIN1_ACT_INFO 0x0088
510 #define RK3399_WIN1_DSP_INFO 0x008c
511 #define RK3399_WIN1_DSP_ST 0x0090
512 #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094
513 #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098
514 #define RK3399_WIN1_SCL_OFFSET 0x009c
515 #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0
516 #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4
517 #define RK3399_WIN1_FADING_CTRL 0x00a8
518 #define RK3399_WIN1_CTRL2 0x00ac
519 #define RK3399_WIN2_CTRL0 0x00b0
520 #define RK3399_WIN2_CTRL1 0x00b4
521 #define RK3399_WIN2_VIR0_1 0x00b8
522 #define RK3399_WIN2_VIR2_3 0x00bc
523 #define RK3399_WIN2_MST0 0x00c0
524 #define RK3399_WIN2_DSP_INFO0 0x00c4
525 #define RK3399_WIN2_DSP_ST0 0x00c8
526 #define RK3399_WIN2_COLOR_KEY 0x00cc
527 #define RK3399_WIN2_MST1 0x00d0
528 #define RK3399_WIN2_DSP_INFO1 0x00d4
529 #define RK3399_WIN2_DSP_ST1 0x00d8
530 #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc
531 #define RK3399_WIN2_MST2 0x00e0
532 #define RK3399_WIN2_DSP_INFO2 0x00e4
533 #define RK3399_WIN2_DSP_ST2 0x00e8
534 #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec
535 #define RK3399_WIN2_MST3 0x00f0
536 #define RK3399_WIN2_DSP_INFO3 0x00f4
537 #define RK3399_WIN2_DSP_ST3 0x00f8
538 #define RK3399_WIN2_FADING_CTRL 0x00fc
539 #define RK3399_WIN3_CTRL0 0x0100
540 #define RK3399_WIN3_CTRL1 0x0104
541 #define RK3399_WIN3_VIR0_1 0x0108
542 #define RK3399_WIN3_VIR2_3 0x010c
543 #define RK3399_WIN3_MST0 0x0110
544 #define RK3399_WIN3_DSP_INFO0 0x0114
545 #define RK3399_WIN3_DSP_ST0 0x0118
546 #define RK3399_WIN3_COLOR_KEY 0x011c
547 #define RK3399_WIN3_MST1 0x0120
548 #define RK3399_WIN3_DSP_INFO1 0x0124
549 #define RK3399_WIN3_DSP_ST1 0x0128
550 #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c
551 #define RK3399_WIN3_MST2 0x0130
552 #define RK3399_WIN3_DSP_INFO2 0x0134
553 #define RK3399_WIN3_DSP_ST2 0x0138
554 #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c
555 #define RK3399_WIN3_MST3 0x0140
556 #define RK3399_WIN3_DSP_INFO3 0x0144
557 #define RK3399_WIN3_DSP_ST3 0x0148
558 #define RK3399_WIN3_FADING_CTRL 0x014c
559 #define RK3399_HWC_CTRL0 0x0150
560 #define RK3399_HWC_CTRL1 0x0154
561 #define RK3399_HWC_MST 0x0158
562 #define RK3399_HWC_DSP_ST 0x015c
563 #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160
564 #define RK3399_HWC_DST_ALPHA_CTRL 0x0164
565 #define RK3399_HWC_FADING_CTRL 0x0168
566 #define RK3399_HWC_RESERVED1 0x016c
567 #define RK3399_POST_DSP_HACT_INFO 0x0170
568 #define RK3399_POST_DSP_VACT_INFO 0x0174
569 #define RK3399_POST_SCL_FACTOR_YRGB 0x0178
570 #define RK3399_POST_RESERVED 0x017c
571 #define RK3399_POST_SCL_CTRL 0x0180
572 #define RK3399_POST_DSP_VACT_INFO_F1 0x0184
573 #define RK3399_DSP_HTOTAL_HS_END 0x0188
574 #define RK3399_DSP_HACT_ST_END 0x018c
575 #define RK3399_DSP_VTOTAL_VS_END 0x0190
576 #define RK3399_DSP_VACT_ST_END 0x0194
577 #define RK3399_DSP_VS_ST_END_F1 0x0198
578 #define RK3399_DSP_VACT_ST_END_F1 0x019c
579 #define RK3399_PWM_CTRL 0x01a0
580 #define RK3399_PWM_PERIOD_HPR 0x01a4
581 #define RK3399_PWM_DUTY_LPR 0x01a8
582 #define RK3399_PWM_CNT 0x01ac
583 #define RK3399_BCSH_COLOR_BAR 0x01b0
584 #define RK3399_BCSH_BCS 0x01b4
585 #define RK3399_BCSH_H 0x01b8
586 #define RK3399_BCSH_CTRL 0x01bc
587 #define RK3399_CABC_CTRL0 0x01c0
588 #define RK3399_CABC_CTRL1 0x01c4
589 #define RK3399_CABC_CTRL2 0x01c8
590 #define RK3399_CABC_CTRL3 0x01cc
591 #define RK3399_CABC_GAUSS_LINE0_0 0x01d0
592 #define RK3399_CABC_GAUSS_LINE0_1 0x01d4
593 #define RK3399_CABC_GAUSS_LINE1_0 0x01d8
594 #define RK3399_CABC_GAUSS_LINE1_1 0x01dc
595 #define RK3399_CABC_GAUSS_LINE2_0 0x01e0
596 #define RK3399_CABC_GAUSS_LINE2_1 0x01e4
597 #define RK3399_FRC_LOWER01_0 0x01e8
598 #define RK3399_FRC_LOWER01_1 0x01ec
599 #define RK3399_FRC_LOWER10_0 0x01f0
600 #define RK3399_FRC_LOWER10_1 0x01f4
601 #define RK3399_FRC_LOWER11_0 0x01f8
602 #define RK3399_FRC_LOWER11_1 0x01fc
603 #define RK3399_AFBCD0_CTRL 0x0200
604 #define RK3399_AFBCD0_HDR_PTR 0x0204
605 #define RK3399_AFBCD0_PIC_SIZE 0x0208
606 #define RK3399_AFBCD0_STATUS 0x020c
607 #define RK3399_AFBCD1_CTRL 0x0220
608 #define RK3399_AFBCD1_HDR_PTR 0x0224
609 #define RK3399_AFBCD1_PIC_SIZE 0x0228
610 #define RK3399_AFBCD1_STATUS 0x022c
611 #define RK3399_AFBCD2_CTRL 0x0240
612 #define RK3399_AFBCD2_HDR_PTR 0x0244
613 #define RK3399_AFBCD2_PIC_SIZE 0x0248
614 #define RK3399_AFBCD2_STATUS 0x024c
615 #define RK3399_AFBCD3_CTRL 0x0260
616 #define RK3399_AFBCD3_HDR_PTR 0x0264
617 #define RK3399_AFBCD3_PIC_SIZE 0x0268
618 #define RK3399_AFBCD3_STATUS 0x026c
619 #define RK3399_INTR_EN0 0x0280
620 #define RK3399_INTR_CLEAR0 0x0284
621 #define RK3399_INTR_STATUS0 0x0288
622 #define RK3399_INTR_RAW_STATUS0 0x028c
623 #define RK3399_INTR_EN1 0x0290
624 #define RK3399_INTR_CLEAR1 0x0294
625 #define RK3399_INTR_STATUS1 0x0298
626 #define RK3399_INTR_RAW_STATUS1 0x029c
627 #define RK3399_LINE_FLAG 0x02a0
628 #define RK3399_VOP_STATUS 0x02a4
629 #define RK3399_BLANKING_VALUE 0x02a8
630 #define RK3399_MCU_BYPASS_PORT 0x02ac
631 #define RK3399_WIN0_DSP_BG 0x02b0
632 #define RK3399_WIN1_DSP_BG 0x02b4
633 #define RK3399_WIN2_DSP_BG 0x02b8
634 #define RK3399_WIN3_DSP_BG 0x02bc
635 #define RK3399_YUV2YUV_WIN 0x02c0
636 #define RK3399_YUV2YUV_POST 0x02c4
637 #define RK3399_AUTO_GATING_EN 0x02cc
638 #define RK3399_WIN0_CSC_COE 0x03a0
639 #define RK3399_WIN1_CSC_COE 0x03c0
640 #define RK3399_WIN2_CSC_COE 0x03e0
641 #define RK3399_WIN3_CSC_COE 0x0400
642 #define RK3399_HWC_CSC_COE 0x0420
643 #define RK3399_BCSH_R2Y_CSC_COE 0x0440
644 #define RK3399_BCSH_Y2R_CSC_COE 0x0460
645 #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480
646 #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0
647 #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0
648 #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0
649 #define RK3399_WIN0_YUV2YUV_3X3 0x0500
650 #define RK3399_WIN0_YUV2YUV_R2Y 0x0520
651 #define RK3399_WIN1_YUV2YUV_Y2R 0x0540
652 #define RK3399_WIN1_YUV2YUV_3X3 0x0560
653 #define RK3399_WIN1_YUV2YUV_R2Y 0x0580
654 #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0
655 #define RK3399_WIN2_YUV2YUV_3X3 0x05c0
656 #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0
657 #define RK3399_WIN3_YUV2YUV_Y2R 0x0600
658 #define RK3399_WIN3_YUV2YUV_3X3 0x0620
659 #define RK3399_WIN3_YUV2YUV_R2Y 0x0640
660 #define RK3399_WIN2_LUT_ADDR 0x1000
661 #define RK3399_WIN3_LUT_ADDR 0x1400
662 #define RK3399_HWC_LUT_ADDR 0x1800
663 #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00
664 #define RK3399_GAMMA_LUT_ADDR 0x2000
668 #define RK3328_REG_CFG_DONE 0x00000000
669 #define RK3328_VERSION_INFO 0x00000004
670 #define RK3328_SYS_CTRL 0x00000008
671 #define RK3328_SYS_CTRL1 0x0000000c
672 #define RK3328_DSP_CTRL0 0x00000010
673 #define RK3328_DSP_CTRL1 0x00000014
674 #define RK3328_DSP_BG 0x00000018
675 #define RK3328_AUTO_GATING_EN 0x0000003c
676 #define RK3328_LINE_FLAG 0x00000040
677 #define RK3328_VOP_STATUS 0x00000044
678 #define RK3328_BLANKING_VALUE 0x00000048
679 #define RK3328_WIN0_DSP_BG 0x00000050
680 #define RK3328_WIN1_DSP_BG 0x00000054
681 #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0
682 #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4
683 #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8
684 #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc
685 #define RK3328_INTR_EN0 0x000000e0
686 #define RK3328_INTR_CLEAR0 0x000000e4
687 #define RK3328_INTR_STATUS0 0x000000e8
688 #define RK3328_INTR_RAW_STATUS0 0x000000ec
689 #define RK3328_INTR_EN1 0x000000f0
690 #define RK3328_INTR_CLEAR1 0x000000f4
691 #define RK3328_INTR_STATUS1 0x000000f8
692 #define RK3328_INTR_RAW_STATUS1 0x000000fc
693 #define RK3328_WIN0_CTRL0 0x00000100
694 #define RK3328_WIN0_CTRL1 0x00000104
695 #define RK3328_WIN0_COLOR_KEY 0x00000108
696 #define RK3328_WIN0_VIR 0x0000010c
697 #define RK3328_WIN0_YRGB_MST 0x00000110
698 #define RK3328_WIN0_CBR_MST 0x00000114
699 #define RK3328_WIN0_ACT_INFO 0x00000118
700 #define RK3328_WIN0_DSP_INFO 0x0000011c
701 #define RK3328_WIN0_DSP_ST 0x00000120
702 #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124
703 #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128
704 #define RK3328_WIN0_SCL_OFFSET 0x0000012c
705 #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130
706 #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134
707 #define RK3328_WIN0_FADING_CTRL 0x00000138
708 #define RK3328_WIN0_CTRL2 0x0000013c
709 #define RK3328_DBG_WIN0_REG0 0x000001f0
710 #define RK3328_DBG_WIN0_REG1 0x000001f4
711 #define RK3328_DBG_WIN0_REG2 0x000001f8
712 #define RK3328_DBG_WIN0_RESERVED 0x000001fc
713 #define RK3328_WIN1_CTRL0 0x00000200
714 #define RK3328_WIN1_CTRL1 0x00000204
715 #define RK3328_WIN1_COLOR_KEY 0x00000208
716 #define RK3328_WIN1_VIR 0x0000020c
717 #define RK3328_WIN1_YRGB_MST 0x00000210
718 #define RK3328_WIN1_CBR_MST 0x00000214
719 #define RK3328_WIN1_ACT_INFO 0x00000218
720 #define RK3328_WIN1_DSP_INFO 0x0000021c
721 #define RK3328_WIN1_DSP_ST 0x00000220
722 #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224
723 #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228
724 #define RK3328_WIN1_SCL_OFFSET 0x0000022c
725 #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230
726 #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234
727 #define RK3328_WIN1_FADING_CTRL 0x00000238
728 #define RK3328_WIN1_CTRL2 0x0000023c
729 #define RK3328_DBG_WIN1_REG0 0x000002f0
730 #define RK3328_DBG_WIN1_REG1 0x000002f4
731 #define RK3328_DBG_WIN1_REG2 0x000002f8
732 #define RK3328_DBG_WIN1_RESERVED 0x000002fc
733 #define RK3328_WIN2_CTRL0 0x00000300
734 #define RK3328_WIN2_CTRL1 0x00000304
735 #define RK3328_WIN2_COLOR_KEY 0x00000308
736 #define RK3328_WIN2_VIR 0x0000030c
737 #define RK3328_WIN2_YRGB_MST 0x00000310
738 #define RK3328_WIN2_CBR_MST 0x00000314
739 #define RK3328_WIN2_ACT_INFO 0x00000318
740 #define RK3328_WIN2_DSP_INFO 0x0000031c
741 #define RK3328_WIN2_DSP_ST 0x00000320
742 #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324
743 #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328
744 #define RK3328_WIN2_SCL_OFFSET 0x0000032c
745 #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330
746 #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334
747 #define RK3328_WIN2_FADING_CTRL 0x00000338
748 #define RK3328_WIN2_CTRL2 0x0000033c
749 #define RK3328_DBG_WIN2_REG0 0x000003f0
750 #define RK3328_DBG_WIN2_REG1 0x000003f4
751 #define RK3328_DBG_WIN2_REG2 0x000003f8
752 #define RK3328_DBG_WIN2_RESERVED 0x000003fc
753 #define RK3328_WIN3_CTRL0 0x00000400
754 #define RK3328_WIN3_CTRL1 0x00000404
755 #define RK3328_WIN3_COLOR_KEY 0x00000408
756 #define RK3328_WIN3_VIR 0x0000040c
757 #define RK3328_WIN3_YRGB_MST 0x00000410
758 #define RK3328_WIN3_CBR_MST 0x00000414
759 #define RK3328_WIN3_ACT_INFO 0x00000418
760 #define RK3328_WIN3_DSP_INFO 0x0000041c
761 #define RK3328_WIN3_DSP_ST 0x00000420
762 #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424
763 #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428
764 #define RK3328_WIN3_SCL_OFFSET 0x0000042c
765 #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430
766 #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434
767 #define RK3328_WIN3_FADING_CTRL 0x00000438
768 #define RK3328_WIN3_CTRL2 0x0000043c
769 #define RK3328_DBG_WIN3_REG0 0x000004f0
770 #define RK3328_DBG_WIN3_REG1 0x000004f4
771 #define RK3328_DBG_WIN3_REG2 0x000004f8
772 #define RK3328_DBG_WIN3_RESERVED 0x000004fc
774 #define RK3328_HWC_CTRL0 0x00000500
775 #define RK3328_HWC_CTRL1 0x00000504
776 #define RK3328_HWC_MST 0x00000508
777 #define RK3328_HWC_DSP_ST 0x0000050c
778 #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510
779 #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514
780 #define RK3328_HWC_FADING_CTRL 0x00000518
781 #define RK3328_HWC_RESERVED1 0x0000051c
782 #define RK3328_POST_DSP_HACT_INFO 0x00000600
783 #define RK3328_POST_DSP_VACT_INFO 0x00000604
784 #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608
785 #define RK3328_POST_RESERVED 0x0000060c
786 #define RK3328_POST_SCL_CTRL 0x00000610
787 #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614
788 #define RK3328_DSP_HTOTAL_HS_END 0x00000618
789 #define RK3328_DSP_HACT_ST_END 0x0000061c
790 #define RK3328_DSP_VTOTAL_VS_END 0x00000620
791 #define RK3328_DSP_VACT_ST_END 0x00000624
792 #define RK3328_DSP_VS_ST_END_F1 0x00000628
793 #define RK3328_DSP_VACT_ST_END_F1 0x0000062c
794 #define RK3328_BCSH_COLOR_BAR 0x00000640
795 #define RK3328_BCSH_BCS 0x00000644
796 #define RK3328_BCSH_H 0x00000648
797 #define RK3328_BCSH_CTRL 0x0000064c
798 #define RK3328_FRC_LOWER01_0 0x00000678
799 #define RK3328_FRC_LOWER01_1 0x0000067c
800 #define RK3328_FRC_LOWER10_0 0x00000680
801 #define RK3328_FRC_LOWER10_1 0x00000684
802 #define RK3328_FRC_LOWER11_0 0x00000688
803 #define RK3328_FRC_LOWER11_1 0x0000068c
804 #define RK3328_DBG_POST_REG0 0x000006e8
805 #define RK3328_DBG_POST_RESERVED 0x000006ec
806 #define RK3328_DBG_DATAO 0x000006f0
807 #define RK3328_DBG_DATAO_2 0x000006f4
810 #define RK3328_SDR2HDR_CTRL 0x00000700
811 #define RK3328_EOTF_OETF_Y0 0x00000704
812 #define RK3328_RESERVED0001 0x00000708
813 #define RK3328_RESERVED0002 0x0000070c
814 #define RK3328_EOTF_OETF_Y1 0x00000710
815 #define RK3328_EOTF_OETF_Y64 0x0000080c
816 #define RK3328_OETF_DX_DXPOW1 0x00000810
817 #define RK3328_OETF_DX_DXPOW64 0x0000090c
818 #define RK3328_OETF_XN1 0x00000910
819 #define RK3328_OETF_XN63 0x00000a08
822 #define RK3328_HDR2SDR_CTRL 0x00000a10
823 #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14
824 #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18
825 #define RK3328_RESERVED0003 0x00000a1c
826 #define RK3328_HDR2SDR_DST_RANGE 0x00000a20
827 #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24
828 #define RK3328_EETF_OETF_Y0 0x00000a28
829 #define RK3328_SAT_Y0 0x00000a2c
830 #define RK3328_EETF_OETF_Y1 0x00000a30
831 #define RK3328_SAT_Y1 0x00000ab0
832 #define RK3328_SAT_Y8 0x00000acc
834 #define RK3328_HWC_LUT_ADDR 0x00000c00
837 #define RK3036_SYS_CTRL 0x00
838 #define RK3036_DSP_CTRL0 0x04
839 #define RK3036_DSP_CTRL1 0x08
840 #define RK3036_INT_SCALER 0x0c
841 #define RK3036_INT_STATUS 0x10
842 #define RK3036_ALPHA_CTRL 0x14
843 #define RK3036_WIN0_COLOR_KEY 0x18
844 #define RK3036_WIN1_COLOR_KEY 0x1c
845 #define RK3036_WIN0_YRGB_MST 0x20
846 #define RK3036_WIN0_CBR_MST 0x24
847 #define RK3036_WIN1_VIR 0x28
848 #define RK3036_AXI_BUS_CTRL 0x2c
849 #define RK3036_WIN0_VIR 0x30
850 #define RK3036_WIN0_ACT_INFO 0x34
851 #define RK3036_WIN0_DSP_INFO 0x38
852 #define RK3036_WIN0_DSP_ST 0x3c
853 #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
854 #define RK3036_WIN0_SCL_FACTOR_CBR 0x44
855 #define RK3036_WIN0_SCL_OFFSET 0x48
856 #define RK3036_HWC_MST 0x58
857 #define RK3036_HWC_DSP_ST 0x5c
858 #define RK3036_DSP_HTOTAL_HS_END 0x6c
859 #define RK3036_DSP_HACT_ST_END 0x70
860 #define RK3036_DSP_VTOTAL_VS_END 0x74
861 #define RK3036_DSP_VACT_ST_END 0x78
862 #define RK3036_DSP_VS_ST_END_F1 0x7c
863 #define RK3036_DSP_VACT_ST_END_F1 0x80
864 #define RK3036_GATHER_TRANSFER 0x84
865 #define RK3036_VERSION_INFO 0x94
866 #define RK3036_REG_CFG_DONE 0x90
867 #define RK3036_WIN1_MST 0xa0
868 #define RK3036_WIN1_ACT_INFO 0xb4
869 #define RK3036_WIN1_DSP_INFO 0xb8
870 #define RK3036_WIN1_DSP_ST 0xbc
871 #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
872 #define RK3036_WIN1_SCL_OFFSET 0xc8
873 #define RK3036_BCSH_CTRL 0xd0
874 #define RK3036_BCSH_COLOR_BAR 0xd4
875 #define RK3036_BCSH_BCS 0xd8
876 #define RK3036_BCSH_H 0xdc
877 #define RK3036_WIN1_LUT_ADDR 0x400
878 #define RK3036_HWC_LUT_ADDR 0x800
882 #define RK3126_WIN1_MST 0x0004c
883 #define RK3126_WIN1_DSP_INFO 0x00050
884 #define RK3126_WIN1_DSP_ST 0x00054
888 #define RK3366_LIT_REG_CFG_DONE 0x00000
889 #define RK3366_LIT_VERSION 0x00004
890 #define RK3366_LIT_DSP_BG 0x00008
891 #define RK3366_LIT_MCU_CTRL 0x0000c
892 #define RK3366_LIT_SYS_CTRL0 0x00010
893 #define RK3366_LIT_SYS_CTRL1 0x00014
894 #define RK3366_LIT_SYS_CTRL2 0x00018
895 #define RK3366_LIT_DSP_CTRL0 0x00020
896 #define RK3366_LIT_DSP_CTRL2 0x00028
897 #define RK3366_LIT_VOP_STATUS 0x0002c
898 #define RK3366_LIT_LINE_FLAG 0x00030
899 #define RK3366_LIT_INTR_EN 0x00034
900 #define RK3366_LIT_INTR_CLEAR 0x00038
901 #define RK3366_LIT_INTR_STATUS 0x0003c
902 #define RK3366_LIT_WIN0_CTRL0 0x00050
903 #define RK3366_LIT_WIN0_CTRL1 0x00054
904 #define RK3366_LIT_WIN0_COLOR_KEY 0x00058
905 #define RK3366_LIT_WIN0_VIR 0x0005c
906 #define RK3366_LIT_WIN0_YRGB_MST0 0x00060
907 #define RK3366_LIT_WIN0_CBR_MST0 0x00064
908 #define RK3366_LIT_WIN0_ACT_INFO 0x00068
909 #define RK3366_LIT_WIN0_DSP_INFO 0x0006c
910 #define RK3366_LIT_WIN0_DSP_ST 0x00070
911 #define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074
912 #define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078
913 #define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c
914 #define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080
915 #define RK3366_LIT_WIN1_CTRL0 0x00090
916 #define RK3366_LIT_WIN1_CTRL1 0x00094
917 #define RK3366_LIT_WIN1_VIR 0x00098
918 #define RK3366_LIT_WIN1_MST 0x000a0
919 #define RK3366_LIT_WIN1_DSP_INFO 0x000a4
920 #define RK3366_LIT_WIN1_DSP_ST 0x000a8
921 #define RK3366_LIT_WIN1_COLOR_KEY 0x000ac
922 #define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc
923 #define RK3366_LIT_HWC_CTRL0 0x000e0
924 #define RK3366_LIT_HWC_CTRL1 0x000e4
925 #define RK3366_LIT_HWC_MST 0x000e8
926 #define RK3366_LIT_HWC_DSP_ST 0x000ec
927 #define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0
928 #define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100
929 #define RK3366_LIT_DSP_HACT_ST_END 0x00104
930 #define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108
931 #define RK3366_LIT_DSP_VACT_ST_END 0x0010c
932 #define RK3366_LIT_DSP_VS_ST_END_F1 0x00110
933 #define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114
934 #define RK3366_LIT_BCSH_CTRL 0x00160
935 #define RK3366_LIT_BCSH_COL_BAR 0x00164
936 #define RK3366_LIT_BCSH_BCS 0x00168
937 #define RK3366_LIT_BCSH_H 0x0016c
938 #define RK3366_LIT_FRC_LOWER01_0 0x00170
939 #define RK3366_LIT_FRC_LOWER01_1 0x00174
940 #define RK3366_LIT_FRC_LOWER10_0 0x00178
941 #define RK3366_LIT_FRC_LOWER10_1 0x0017c
942 #define RK3366_LIT_FRC_LOWER11_0 0x00180
943 #define RK3366_LIT_FRC_LOWER11_1 0x00184
944 #define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c
945 #define RK3366_LIT_DBG_REG_000 0x00190
946 #define RK3366_LIT_BLANKING_VALUE 0x001f4
947 #define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8
948 #define RK3366_LIT_FLAG_REG 0x001fc
949 #define RK3366_LIT_HWC_LUT_ADDR 0x00600
950 #define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00
954 #define PX30_CABC_CTRL0 0x00200
955 #define PX30_CABC_CTRL1 0x00204
956 #define PX30_CABC_CTRL2 0x00208
957 #define PX30_CABC_CTRL3 0x0020c
958 #define PX30_CABC_GAUSS_LINE0_0 0x00210
959 #define PX30_CABC_GAUSS_LINE0_1 0x00214
960 #define PX30_CABC_GAUSS_LINE1_0 0x00218
961 #define PX30_CABC_GAUSS_LINE1_1 0x0021c
962 #define PX30_CABC_GAUSS_LINE2_0 0x00220
963 #define PX30_CABC_GAUSS_LINE2_1 0x00224
964 #define PX30_AFBCD0_CTRL 0x00240
965 #define PX30_AFBCD0_HDR_PTR 0x00244
966 #define PX30_AFBCD0_PIC_SIZE 0x00248
967 #define PX30_AFBCD0_PIC_OFFSET 0x0024c
968 #define PX30_AFBCD0_AXI_CTRL 0x00250
969 #define PX30_GRF_PD_VO_CON1 0x00438
973 #define RK1808_GRF_PD_VO_CON1 0x00000444
977 #define RV1126_WIN2_CTRL0 0x0190
978 #define RV1126_WIN2_VIR0_1 0x0198
979 #define RV1126_WIN2_MST0 0x01a0
980 #define RV1126_WIN2_DSP_INFO0 0x01a4
981 #define RV1126_WIN2_DSP_ST0 0x01a8