3980 	u32 win_offset = win->reg_offset;  in vop2_setup_scale()  local
4038 		vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
4042 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4044 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4046 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4049 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4052 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4056 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4059 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4065 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4067 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4069 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4071 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4074 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4076 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4078 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4080 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
4084 		vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
4088 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
4090 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
4092 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
4096 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
4098 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
4101 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
4103 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
4106 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
4109 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
4117 	u32 win_offset = win->reg_offset;  in vop2_axi_config()  local
4120 		vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK,  in vop2_axi_config()
4122 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK,  in vop2_axi_config()
4124 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK,  in vop2_axi_config()
4127 		vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK,  in vop2_axi_config()
4129 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK,  in vop2_axi_config()
4131 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK,  in vop2_axi_config()
4165 	u32 win_offset = win->reg_offset;  in vop2_set_cluster_win()  local
4207 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset,  in vop2_set_cluster_win()
4210 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,  in vop2_set_cluster_win()
4213 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir);  in vop2_set_cluster_win()
4214 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset,  in vop2_set_cluster_win()
4217 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info);  in vop2_set_cluster_win()
4218 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info);  in vop2_set_cluster_win()
4219 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st);  in vop2_set_cluster_win()
4221 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
4224 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
4227 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK,  in vop2_set_cluster_win()
4231 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
4234 	vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
4258 	u32 win_offset = win->reg_offset;  in vop2_set_smart_win()  local
4299 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, ESMART_LB_SELECT_MASK,  in vop2_set_smart_win()
4310 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK,  in vop2_set_smart_win()
4313 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_set_smart_win()
4316 	vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir);  in vop2_set_smart_win()
4317 	vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset,  in vop2_set_smart_win()
4320 	vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset,  in vop2_set_smart_win()
4322 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset,  in vop2_set_smart_win()
4324 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st);  in vop2_set_smart_win()
4326 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()
4330 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,  in vop2_set_smart_win()
4333 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK,  in vop2_set_smart_win()
4337 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()