1627 	u32 vp_offset = crtc_id * 0x100;  in rk3568_vop2_load_lut()  local
1637 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset,  in rk3568_vop2_load_lut()
1644 	u32 vp_offset = crtc_id * 0x100;  in rk3588_vop2_load_lut()  local
1654 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset,  in rk3588_vop2_load_lut()
1656 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset,  in rk3588_vop2_load_lut()
1729 	u32 vp_offset = cstate->crtc_id * 0x100;  in rockchip_vop2_cubic_lut_init()  local
1764 	vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset,  in rockchip_vop2_cubic_lut_init()
1768 	vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset,  in rockchip_vop2_cubic_lut_init()
1770 	vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset,  in rockchip_vop2_cubic_lut_init()
1780 	u32 vp_offset = crtc_id * 0x100;  in vop2_bcsh_reg_update()  local
1782 	vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK,  in vop2_bcsh_reg_update()
1784 	vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK,  in vop2_bcsh_reg_update()
1787 	vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK,  in vop2_bcsh_reg_update()
1789 	vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK,  in vop2_bcsh_reg_update()
1793 		vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset,  in vop2_bcsh_reg_update()
1798 	vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset,  in vop2_bcsh_reg_update()
1801 	vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset,  in vop2_bcsh_reg_update()
1803 	vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset,  in vop2_bcsh_reg_update()
1806 	vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset,  in vop2_bcsh_reg_update()
1808 	vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset,  in vop2_bcsh_reg_update()
1810 	vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset,  in vop2_bcsh_reg_update()
1813 	vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset,  in vop2_bcsh_reg_update()
1941 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop2_post_config()  local
1964 	vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val);  in vop2_post_config()
1969 	vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val);  in vop2_post_config()
1972 	vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val);  in vop2_post_config()
1975 	vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset,  in vop2_post_config()
1983 		vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);  in vop2_post_config()
2001 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop3_post_acm_config()  local
2008 	vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_acm_config()
2068 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop3_post_csc_config()  local
2105 		vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_csc_config()
2126 		vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_csc_config()
2130 	vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_csc_config()
2132 	vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_csc_config()
2134 	vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,  in vop3_post_csc_config()
2765 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rk3588_vop2_if_cfg()  local
2836 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
2838 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
2862 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
2864 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
2870 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3588_vop2_if_cfg()
2873 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
2982 	vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3,  in rk3588_vop2_if_cfg()
2984 	vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3,  in rk3588_vop2_if_cfg()
2996 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rk3568_vop2_if_cfg()  local
3092 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3568_vop2_if_cfg()
3095 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3568_vop2_if_cfg()
3213 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop2_post_color_swap()  local
3228 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset,  in vop2_post_color_swap()
3526 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop3_mcu_mode_setup()  local
3528 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_mode_setup()
3530 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_mode_setup()
3532 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,  in vop3_mcu_mode_setup()
3534 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,  in vop3_mcu_mode_setup()
3536 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,  in vop3_mcu_mode_setup()
3538 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,  in vop3_mcu_mode_setup()
3540 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,  in vop3_mcu_mode_setup()
3548 	u32 vp_offset = (cstate->crtc_id * 0x100);  in vop3_mcu_bypass_mode_setup()  local
3550 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_bypass_mode_setup()
3552 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_bypass_mode_setup()
3554 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,  in vop3_mcu_bypass_mode_setup()
3556 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,  in vop3_mcu_bypass_mode_setup()
3558 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,  in vop3_mcu_bypass_mode_setup()
3560 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,  in vop3_mcu_bypass_mode_setup()
3562 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,  in vop3_mcu_bypass_mode_setup()
3572 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rockchip_vop2_send_mcu_cmd()  local
3587 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3595 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3597 		vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,  in rockchip_vop2_send_mcu_cmd()
3600 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3604 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3606 		vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,  in rockchip_vop2_send_mcu_cmd()
3611 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3629 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3667 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rockchip_vop2_init()  local
3726 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK,  in rockchip_vop2_init()
3764 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3766 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3768 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3770 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3779 	vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset,  in rockchip_vop2_init()
3783 	vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
3786 	vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
3792 		vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset,  in rockchip_vop2_init()
3796 		vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val);  in rockchip_vop2_init()
3797 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3799 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3801 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3806 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3808 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3812 	vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,  in rockchip_vop2_init()
3817 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3820 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3824 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_init()
3827 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_init()
3837 	vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val);  in rockchip_vop2_init()
3845 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3849 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
4480 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rockchip_vop2_enable()  local
4483 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_enable()
4495 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_enable()
4505 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rockchip_vop2_disable()  local
4508 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_disable()
4726 	u32 vp_offset = (cstate->crtc_id * 0x100);  in rockchip_vop2_apply_soft_te()  local
4730 	ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,  in rockchip_vop2_apply_soft_te()
4740 				vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_apply_soft_te()