1371 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)  in vop2_writel()  function
1764 	vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset,  in rockchip_vop2_cubic_lut_init()
1906 	vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);  in vop2_setup_dly_for_vp()
1933 	vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);  in vop3_setup_pipe_dly()
1964 	vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val);  in vop2_post_config()
1969 	vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val);  in vop2_post_config()
1972 	vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val);  in vop2_post_config()
1975 	vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset,  in vop2_post_config()
1983 		vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);  in vop2_post_config()
2520 		vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0);  in vop2_global_initial()
3299 		vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++);  in vop2_load_pps()
3468 	vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);  in vop2_dsc_enable()
3473 	vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);  in vop2_dsc_enable()
3589 		vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_send_mcu_cmd()
3779 	vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset,  in rockchip_vop2_init()
3783 	vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
3786 	vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
3792 		vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset,  in rockchip_vop2_init()
3796 		vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val);  in rockchip_vop2_init()
3812 	vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,  in rockchip_vop2_init()
3837 	vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val);  in rockchip_vop2_init()
3842 		vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val);  in rockchip_vop2_init()
4038 		vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
4084 		vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
4213 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir);  in vop2_set_cluster_win()
4214 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset,  in vop2_set_cluster_win()
4217 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info);  in vop2_set_cluster_win()
4218 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info);  in vop2_set_cluster_win()
4219 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st);  in vop2_set_cluster_win()
4236 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in vop2_set_cluster_win()
4316 	vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir);  in vop2_set_smart_win()
4317 	vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset,  in vop2_set_smart_win()
4320 	vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset,  in vop2_set_smart_win()
4322 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset,  in vop2_set_smart_win()
4324 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st);  in vop2_set_smart_win()
4340 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in vop2_set_smart_win()
4489 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_enable()
4514 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_disable()