Lines Matching refs:vop2
1204 struct vop2 { struct
1219 static struct vop2 *rockchip_vop2; argument
1221 static inline bool is_vop3(struct vop2 *vop2) in is_vop3() argument
1223 if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588) in is_vop3()
1349 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) in vop2_get_primary_plane() argument
1353 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_get_primary_plane()
1354 if (plane_mask & BIT(vop2->data->vp_primary_plane_order[i])) in vop2_get_primary_plane()
1355 return vop2->data->vp_primary_plane_order[i]; in vop2_get_primary_plane()
1358 return vop2->data->vp_primary_plane_order[0]; in vop2_get_primary_plane()
1371 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) in vop2_writel() argument
1373 writel(v, vop2->regs + offset); in vop2_writel()
1374 vop2->regsbak[offset >> 2] = v; in vop2_writel()
1377 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) in vop2_readl() argument
1379 return readl(vop2->regs + offset); in vop2_readl()
1382 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, in vop2_mask_write() argument
1392 u32 cached_val = vop2->regsbak[offset >> 2]; in vop2_mask_write()
1395 vop2->regsbak[offset >> 2] = v; in vop2_mask_write()
1398 writel(v, vop2->regs + offset); in vop2_mask_write()
1401 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, in vop2_grf_writel()
1410 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, in vop2_grf_readl()
1600 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) in vop2_find_win_by_phys_id() argument
1604 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_find_win_by_phys_id()
1605 if (vop2->data->win_data[i].phys_id == phys_id) in vop2_find_win_by_phys_id()
1606 return &vop2->data->win_data[i]; in vop2_find_win_by_phys_id()
1612 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) in vop2_find_pd_data_by_id() argument
1616 for (i = 0; i < vop2->data->nr_pd; i++) { in vop2_find_pd_data_by_id()
1617 if (vop2->data->pd[i].id == pd_id) in vop2_find_pd_data_by_id()
1618 return &vop2->data->pd[i]; in vop2_find_pd_data_by_id()
1624 static void rk3568_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3568_vop2_load_lut() argument
1630 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3568_vop2_load_lut()
1637 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3568_vop2_load_lut()
1641 static void rk3588_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3588_vop2_load_lut() argument
1647 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3588_vop2_load_lut()
1654 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1656 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1660 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, in rockchip_vop2_gamma_lut_init() argument
1674 if (gamma_lut_en_num > vop2->data->nr_gammas) { in rockchip_vop2_gamma_lut_init()
1675 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); in rockchip_vop2_gamma_lut_init()
1708 if (vop2->version == VOP_VERSION_RK3568) { in rockchip_vop2_gamma_lut_init()
1709 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1711 } else if (vop2->version == VOP_VERSION_RK3588) { in rockchip_vop2_gamma_lut_init()
1712 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1714 rk3588_vop2_load_lut(vop2, cstate->splice_crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1723 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, in rockchip_vop2_cubic_lut_init() argument
1764 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, in rockchip_vop2_cubic_lut_init()
1766 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, in rockchip_vop2_cubic_lut_init()
1768 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
1770 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
1776 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, in vop2_bcsh_reg_update() argument
1782 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, in vop2_bcsh_reg_update()
1784 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, in vop2_bcsh_reg_update()
1787 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, in vop2_bcsh_reg_update()
1789 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, in vop2_bcsh_reg_update()
1793 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
1798 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
1801 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
1803 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
1806 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
1808 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
1810 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
1813 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
1817 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) in vop2_tv_config_update() argument
1878 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
1880 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); in vop2_tv_config_update()
1883 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop2_setup_dly_for_vp() argument
1893 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; in vop2_setup_dly_for_vp()
1901 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) in vop2_setup_dly_for_vp()
1904 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, in vop2_setup_dly_for_vp()
1906 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop2_setup_dly_for_vp()
1909 static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop3_setup_pipe_dly() argument
1918 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in vop3_setup_pipe_dly()
1921 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); in vop3_setup_pipe_dly()
1923 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL + win_id * 4, in vop3_setup_pipe_dly()
1926 bg_dly = vop2->data->vp_data[crtc_id].win_dly + in vop3_setup_pipe_dly()
1927 vop2->data->vp_data[crtc_id].layer_mix_dly + in vop3_setup_pipe_dly()
1928 vop2->data->vp_data[crtc_id].hdr_mix_dly; in vop3_setup_pipe_dly()
1931 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
1933 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop3_setup_pipe_dly()
1936 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) in vop2_post_config() argument
1964 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); in vop2_post_config()
1969 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); in vop2_post_config()
1972 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); in vop2_post_config()
1975 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, in vop2_post_config()
1983 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); in vop2_post_config()
1986 if (is_vop3(vop2)) { in vop2_post_config()
1987 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
1989 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
1991 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); in vop2_post_config()
1995 static void vop3_post_acm_config(struct display_state *state, struct vop2 *vop2) in vop3_post_acm_config() argument
2008 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_acm_config()
2011 writel(0, vop2->regs + RK3528_ACM_CTRL); in vop3_post_acm_config()
2017 writel(1, vop2->regs + RK3528_ACM_FETCH_START); in vop3_post_acm_config()
2021 writel(value, vop2->regs + RK3528_ACM_CTRL); in vop3_post_acm_config()
2025 writel(value, vop2->regs + RK3528_ACM_DELTA_RANGE); in vop3_post_acm_config()
2033 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2)); in vop3_post_acm_config()
2042 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2)); in vop3_post_acm_config()
2051 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2)); in vop3_post_acm_config()
2054 writel(1, vop2->regs + RK3528_ACM_FETCH_DONE); in vop3_post_acm_config()
2057 static void vop3_post_csc_config(struct display_state *state, struct vop2 *vop2) in vop3_post_csc_config() argument
2105 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2110 writel(value, vop2->regs + RK3528_VP0_CSC_COE01_02); in vop3_post_csc_config()
2113 writel(value, vop2->regs + RK3528_VP0_CSC_COE10_11); in vop3_post_csc_config()
2116 writel(value, vop2->regs + RK3528_VP0_CSC_COE12_20); in vop3_post_csc_config()
2119 writel(value, vop2->regs + RK3528_VP0_CSC_COE21_22); in vop3_post_csc_config()
2120 writel(csc_coef.csc_dc0, vop2->regs + RK3528_VP0_CSC_OFFSET0); in vop3_post_csc_config()
2121 writel(csc_coef.csc_dc1, vop2->regs + RK3528_VP0_CSC_OFFSET1); in vop3_post_csc_config()
2122 writel(csc_coef.csc_dc2, vop2->regs + RK3528_VP0_CSC_OFFSET2); in vop3_post_csc_config()
2126 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2130 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2132 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2134 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2138 static void vop3_post_config(struct display_state *state, struct vop2 *vop2) in vop3_post_config() argument
2154 vop3_post_acm_config(state, vop2); in vop3_post_config()
2155 vop3_post_csc_config(state, vop2); in vop3_post_config()
2164 static int vop2_wait_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) in vop2_wait_power_domain_on() argument
2181 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); in vop2_wait_power_domain_on()
2185 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, in vop2_wait_power_domain_on()
2190 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, in vop2_wait_power_domain_on()
2195 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) in vop2_power_domain_on() argument
2203 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); in vop2_power_domain_on()
2210 ret = vop2_power_domain_on(vop2, pd_data->parent_id); in vop2_power_domain_on()
2217 vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK, in vop2_power_domain_on()
2219 ret = vop2_wait_power_domain_on(vop2, pd_data); in vop2_power_domain_on()
2228 static void rk3588_vop2_regsbak(struct vop2 *vop2) in rk3588_vop2_regsbak() argument
2230 u32 *base = vop2->regs; in rk3588_vop2_regsbak()
2236 for (i = 0; i < (vop2->reg_len >> 2); i++) in rk3588_vop2_regsbak()
2237 vop2->regsbak[i] = base[i]; in rk3588_vop2_regsbak()
2240 static void vop3_overlay_init(struct vop2 *vop2, struct display_state *state) in vop3_overlay_init() argument
2250 for (i = 0; i < vop2->data->nr_vps; i++) { in vop3_overlay_init()
2253 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in vop3_overlay_init()
2255 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in vop3_overlay_init()
2256 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in vop3_overlay_init()
2257 vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + ovl_port_offset, LAYER_SEL_MASK, in vop3_overlay_init()
2264 for (i = 0; i < vop2->data->nr_vps; i++) { in vop3_overlay_init()
2265 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in vop3_overlay_init()
2267 if (!vop2->vp_plane_mask[i].attached_layers[j]) in vop3_overlay_init()
2269 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in vop3_overlay_init()
2270 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in vop3_overlay_init()
2272 vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL_IMD, LAYER_SEL_PORT_MASK, in vop3_overlay_init()
2278 static void vop2_overlay_init(struct vop2 *vop2, struct display_state *state) in vop2_overlay_init() argument
2290 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2291 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in vop2_overlay_init()
2293 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in vop2_overlay_init()
2294 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in vop2_overlay_init()
2295 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, in vop2_overlay_init()
2302 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2303 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in vop2_overlay_init()
2305 if (!vop2->vp_plane_mask[i].attached_layers[j]) in vop2_overlay_init()
2307 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in vop2_overlay_init()
2308 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in vop2_overlay_init()
2310 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, in vop2_overlay_init()
2318 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2320 if (vop2->vp_plane_mask[i].attached_layers_nr) { in vop2_overlay_init()
2321 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; in vop2_overlay_init()
2327 if (i == vop2->data->nr_vps - 1) in vop2_overlay_init()
2328 port_mux = vop2->data->nr_mixers; in vop2_overlay_init()
2330 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; in vop2_overlay_init()
2331 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, in vop2_overlay_init()
2336 static bool vop3_ignore_plane(struct vop2 *vop2, struct vop2_win_data *win) in vop3_ignore_plane() argument
2338 if (!is_vop3(vop2)) in vop3_ignore_plane()
2341 if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE && in vop3_ignore_plane()
2344 else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE && in vop3_ignore_plane()
2347 else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE && in vop3_ignore_plane()
2354 static void vop3_init_esmart_scale_engine(struct vop2 *vop2) in vop3_init_esmart_scale_engine() argument
2361 for (i = 0; i < vop2->data->nr_layers; i++) { in vop3_init_esmart_scale_engine()
2362 win_data = &vop2->data->win_data[i]; in vop3_init_esmart_scale_engine()
2363 if (win_data->type == CLUSTER_LAYER || vop3_ignore_plane(vop2, win_data)) in vop3_init_esmart_scale_engine()
2370 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) in vop2_global_initial() argument
2379 if (vop2->global_init) in vop2_global_initial()
2384 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, in vop2_global_initial()
2391 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2393 vop2->vp_plane_mask[i].plane_mask = plane_mask; in vop2_global_initial()
2395 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; in vop2_global_initial()
2398 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); in vop2_global_initial()
2399 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; in vop2_global_initial()
2400 vop2->vp_plane_mask[i].plane_mask = plane_mask; in vop2_global_initial()
2404 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; in vop2_global_initial()
2405 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); in vop2_global_initial()
2413 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2421 plane_mask = vop2->data->plane_mask; in vop2_global_initial()
2427 if (vop2->version == VOP_VERSION_RK3528 && active_vp_num == 1 && in vop2_global_initial()
2431 if (vop2->version == VOP_VERSION_RK3528) { in vop2_global_initial()
2438 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2440 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ in vop2_global_initial()
2449 vop2->vp_plane_mask[0] = plane_mask[0]; in vop2_global_initial()
2456 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2459 vop2->vp_plane_mask[i] = plane_mask[j++]; in vop2_global_initial()
2463 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2464 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in vop2_global_initial()
2466 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in vop2_global_initial()
2467 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); in vop2_global_initial()
2472 if (vop2->version == VOP_VERSION_RK3588) in vop2_global_initial()
2473 rk3588_vop2_regsbak(vop2); in vop2_global_initial()
2475 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); in vop2_global_initial()
2477 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, in vop2_global_initial()
2479 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in vop2_global_initial()
2482 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2483 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); in vop2_global_initial()
2484 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) in vop2_global_initial()
2485 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); in vop2_global_initial()
2486 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); in vop2_global_initial()
2489 if (is_vop3(vop2)) in vop2_global_initial()
2490 vop3_overlay_init(vop2, state); in vop2_global_initial()
2492 vop2_overlay_init(vop2, state); in vop2_global_initial()
2494 if (is_vop3(vop2)) { in vop2_global_initial()
2507 ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode); in vop2_global_initial()
2509 vop2->esmart_lb_mode = vop2->data->esmart_lb_mode; in vop2_global_initial()
2510 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, ESMART_LB_MODE_SEL_MASK, in vop2_global_initial()
2511 ESMART_LB_MODE_SEL_SHIFT, vop2->esmart_lb_mode, false); in vop2_global_initial()
2513 vop3_init_esmart_scale_engine(vop2); in vop2_global_initial()
2515 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, in vop2_global_initial()
2519 if (vop2->version == VOP_VERSION_RK3568) in vop2_global_initial()
2520 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); in vop2_global_initial()
2522 vop2->global_init = true; in vop2_global_initial()
2525 static int vop2_initial(struct vop2 *vop2, struct display_state *state) in vop2_initial() argument
2527 rockchip_vop2_gamma_lut_init(vop2, state); in vop2_initial()
2528 rockchip_vop2_cubic_lut_init(vop2, state); in vop2_initial()
2543 rockchip_vop2 = calloc(1, sizeof(struct vop2)); in rockchip_vop2_preinit()
2546 memset(rockchip_vop2, 0, sizeof(struct vop2)); in rockchip_vop2_preinit()
2614 struct vop2 *vop2 = cstate->private; in vop2_calc_cru_cfg() local
2655 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2659 vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate); in vop2_calc_cru_cfg()
2680 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2683 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate); in vop2_calc_cru_cfg()
2700 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2703 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate); in vop2_calc_cru_cfg()
2764 struct vop2 *vop2 = cstate->private; in rk3588_vop2_if_cfg() local
2784 if (!vop2->data->nr_dscs) { in rk3588_vop2_if_cfg()
2805 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2810 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2815 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2826 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2829 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, in rk3588_vop2_if_cfg()
2831 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); in rk3588_vop2_if_cfg()
2832 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2836 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
2838 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
2851 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2854 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, in rk3588_vop2_if_cfg()
2856 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, in rk3588_vop2_if_cfg()
2858 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2862 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
2864 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
2870 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3588_vop2_if_cfg()
2873 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
2878 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2882 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2886 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2890 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
2899 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, in rk3588_vop2_if_cfg()
2901 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
2903 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2906 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2909 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
2914 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, in rk3588_vop2_if_cfg()
2916 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
2918 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2921 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2924 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
2929 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, in rk3588_vop2_if_cfg()
2931 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
2933 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2936 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2939 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
2941 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, in rk3588_vop2_if_cfg()
2947 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, in rk3588_vop2_if_cfg()
2949 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
2951 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2954 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
2957 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
2959 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, in rk3588_vop2_if_cfg()
2965 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, in rk3588_vop2_if_cfg()
2967 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
2969 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
2974 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, in rk3588_vop2_if_cfg()
2976 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
2978 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
2982 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
2984 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
2995 struct vop2 *vop2 = cstate->private; in rk3568_vop2_if_cfg() local
3005 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
3007 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3009 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
3011 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
3016 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
3018 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, in rk3568_vop2_if_cfg()
3020 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3022 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
3027 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3568_vop2_if_cfg()
3029 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3031 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
3036 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3568_vop2_if_cfg()
3038 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3040 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
3042 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3047 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, in rk3568_vop2_if_cfg()
3049 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3051 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
3053 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3060 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_if_cfg()
3064 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_if_cfg()
3068 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_if_cfg()
3073 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3568_vop2_if_cfg()
3075 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3077 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3082 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, in rk3568_vop2_if_cfg()
3084 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3086 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3092 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_if_cfg()
3095 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3568_vop2_if_cfg()
3101 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, in rk3568_vop2_if_cfg()
3103 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3105 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3107 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK, in rk3568_vop2_if_cfg()
3112 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3568_vop2_if_cfg()
3114 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
3116 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
3118 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3568_vop2_if_cfg()
3131 struct vop2 *vop2 = cstate->private; in rk3528_vop2_if_cfg() local
3138 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3528_vop2_if_cfg()
3140 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
3145 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3528_vop2_if_cfg()
3147 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
3149 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3528_vop2_if_cfg()
3151 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3528_vop2_if_cfg()
3164 struct vop2 *vop2 = cstate->private; in rk3562_vop2_if_cfg() local
3173 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3562_vop2_if_cfg()
3175 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
3177 vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK, in rk3562_vop2_if_cfg()
3179 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
3184 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3562_vop2_if_cfg()
3186 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
3188 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
3190 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
3195 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3562_vop2_if_cfg()
3197 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
3199 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
3201 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
3212 struct vop2 *vop2 = cstate->private; in vop2_post_color_swap() local
3221 if (vop2->version == VOP_VERSION_RK3588 && in vop2_post_color_swap()
3228 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in vop2_post_color_swap()
3270 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) in vop2_load_pps() argument
3275 const struct vop2_data *vop2_data = vop2->data; in vop2_load_pps()
3299 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); in vop2_load_pps()
3302 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rat… in vop2_dsc_enable() argument
3308 const struct vop2_data *vop2_data = vop2->data; in vop2_dsc_enable()
3328 if (!vop2->data->nr_dscs) { in vop2_dsc_enable()
3338 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) in vop2_dsc_enable()
3342 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
3344 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, in vop2_dsc_enable()
3357 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
3360 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
3365 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, in vop2_dsc_enable()
3367 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, in vop2_dsc_enable()
3369 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, in vop2_dsc_enable()
3371 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, in vop2_dsc_enable()
3373 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
3375 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
3377 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
3429 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, in vop2_dsc_enable()
3431 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, in vop2_dsc_enable()
3447 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, in vop2_dsc_enable()
3453 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, in vop2_dsc_enable()
3456 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, in vop2_dsc_enable()
3458 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, in vop2_dsc_enable()
3462 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, in vop2_dsc_enable()
3468 vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); in vop2_dsc_enable()
3470 vop2_load_pps(state, vop2, dsc_id); in vop2_dsc_enable()
3473 vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); in vop2_dsc_enable()
3485 struct vop2 *vop2 = cstate->private; in is_extend_pll() local
3491 if (vop2->version != VOP_VERSION_RK3588) in is_extend_pll()
3525 struct vop2 *vop2 = cstate->private; in vop3_mcu_mode_setup() local
3528 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
3530 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
3532 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_mode_setup()
3534 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_mode_setup()
3536 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_mode_setup()
3538 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_mode_setup()
3540 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_mode_setup()
3547 struct vop2 *vop2 = cstate->private; in vop3_mcu_bypass_mode_setup() local
3550 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
3552 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
3554 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_bypass_mode_setup()
3556 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_bypass_mode_setup()
3558 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_bypass_mode_setup()
3560 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_bypass_mode_setup()
3562 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_bypass_mode_setup()
3571 struct vop2 *vop2 = cstate->private; in rockchip_vop2_send_mcu_cmd() local
3582 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3584 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3587 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3589 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_send_mcu_cmd()
3595 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3597 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
3600 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3604 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3606 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
3611 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3624 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3626 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3629 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
3655 struct vop2 *vop2 = cstate->private; in rockchip_vop2_init() local
3694 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
3701 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, in rockchip_vop2_init()
3705 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
3707 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
3710 vop2_initial(vop2, state); in rockchip_vop2_init()
3711 if (vop2->version == VOP_VERSION_RK3588) in rockchip_vop2_init()
3713 else if (vop2->version == VOP_VERSION_RK3568) in rockchip_vop2_init()
3715 else if (vop2->version == VOP_VERSION_RK3528) in rockchip_vop2_init()
3717 else if (vop2->version == VOP_VERSION_RK3562) in rockchip_vop2_init()
3726 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, in rockchip_vop2_init()
3764 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3766 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3768 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3770 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3774 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
3779 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, in rockchip_vop2_init()
3783 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); in rockchip_vop2_init()
3786 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); in rockchip_vop2_init()
3792 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, in rockchip_vop2_init()
3796 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); in rockchip_vop2_init()
3797 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3799 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3801 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3806 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3808 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3812 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, in rockchip_vop2_init()
3817 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3820 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3824 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
3827 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
3830 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
3837 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); in rockchip_vop2_init()
3839 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
3842 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); in rockchip_vop2_init()
3845 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3849 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
3852 vop2_tv_config_update(state, vop2); in rockchip_vop2_init()
3853 vop2_post_config(state, vop2); in rockchip_vop2_init()
3855 vop3_post_config(state, vop2); in rockchip_vop2_init()
3859 vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL); in rockchip_vop2_init()
3860 vop2_dsc_enable(state, vop2, 1, dclk_rate * 1000LL); in rockchip_vop2_init()
3862 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL); in rockchip_vop2_init()
3889 if (vop2->version == VOP_VERSION_RK3528) { in rockchip_vop2_init()
3928 if (vop2->version == VOP_VERSION_RK3528) { in rockchip_vop2_init()
3952 if (vop2->version == VOP_VERSION_RK3528 && in rockchip_vop2_init()
3960 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
3962 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
3971 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, in vop2_setup_scale() argument
3984 if (is_vop3(vop2)) { in vop2_setup_scale()
4019 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) { in vop2_setup_scale()
4024 if (is_vop3(vop2)) { in vop2_setup_scale()
4038 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, in vop2_setup_scale()
4041 if (is_vop3(vop2)) { in vop2_setup_scale()
4042 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4044 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4046 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4049 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4052 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4056 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4059 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4064 if (!is_vop3(vop2) || win->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) { in vop2_setup_scale()
4065 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4067 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4069 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4071 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4074 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4076 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4078 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4080 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
4084 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, in vop2_setup_scale()
4087 if (is_vop3(vop2)) { in vop2_setup_scale()
4088 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
4090 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
4092 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
4096 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
4098 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
4101 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
4103 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
4106 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
4109 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
4115 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) in vop2_axi_config() argument
4120 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, in vop2_axi_config()
4122 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, in vop2_axi_config()
4124 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, in vop2_axi_config()
4127 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, in vop2_axi_config()
4129 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, in vop2_axi_config()
4131 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, in vop2_axi_config()
4151 struct vop2 *vop2 = cstate->private; in vop2_set_cluster_win() local
4196 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); in vop2_set_cluster_win()
4198 if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 || in vop2_set_cluster_win()
4199 vop2->version == VOP_VERSION_RK3562) in vop2_set_cluster_win()
4200 vop2_axi_config(vop2, win); in vop2_set_cluster_win()
4206 if (vop2->version == VOP_VERSION_RK3588) in vop2_set_cluster_win()
4207 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset, in vop2_set_cluster_win()
4210 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, in vop2_set_cluster_win()
4213 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); in vop2_set_cluster_win()
4214 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, in vop2_set_cluster_win()
4217 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); in vop2_set_cluster_win()
4218 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); in vop2_set_cluster_win()
4219 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); in vop2_set_cluster_win()
4221 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); in vop2_set_cluster_win()
4224 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
4227 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_cluster_win()
4231 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
4234 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); in vop2_set_cluster_win()
4236 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in vop2_set_cluster_win()
4244 struct vop2 *vop2 = cstate->private; in vop2_set_smart_win() local
4298 if (is_vop3(vop2)) in vop2_set_smart_win()
4299 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, ESMART_LB_SELECT_MASK, in vop2_set_smart_win()
4302 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); in vop2_set_smart_win()
4304 if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 || in vop2_set_smart_win()
4305 vop2->version == VOP_VERSION_RK3562) in vop2_set_smart_win()
4306 vop2_axi_config(vop2, win); in vop2_set_smart_win()
4310 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, in vop2_set_smart_win()
4313 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_set_smart_win()
4316 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); in vop2_set_smart_win()
4317 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, in vop2_set_smart_win()
4320 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, in vop2_set_smart_win()
4322 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, in vop2_set_smart_win()
4324 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); in vop2_set_smart_win()
4326 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
4330 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, in vop2_set_smart_win()
4333 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_smart_win()
4337 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
4340 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in vop2_set_smart_win()
4391 struct vop2 *vop2 = cstate->private; in rockchip_vop2_set_plane() local
4394 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
4403 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); in rockchip_vop2_set_plane()
4410 if (vop3_ignore_plane(vop2, win_data)) in rockchip_vop2_set_plane()
4413 if (vop2->version == VOP_VERSION_RK3588) { in rockchip_vop2_set_plane()
4414 if (vop2_power_domain_on(vop2, win_data->pd_id)) in rockchip_vop2_set_plane()
4420 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); in rockchip_vop2_set_plane()
4423 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) in rockchip_vop2_set_plane()
4461 struct vop2 *vop2 = cstate->private; in vop2_dsc_cfg_done() local
4466 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, in vop2_dsc_cfg_done()
4468 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, in vop2_dsc_cfg_done()
4471 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, in vop2_dsc_cfg_done()
4479 struct vop2 *vop2 = cstate->private; in rockchip_vop2_enable() local
4483 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
4489 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_enable()
4495 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
4504 struct vop2 *vop2 = cstate->private; in rockchip_vop2_disable() local
4508 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_disable()
4514 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_disable()
4522 struct vop2 *vop2 = cstate->private; in rockchip_vop2_get_cursor_plane() local
4534 for (i = 0; i < vop2->data->nr_layers; i++) { in rockchip_vop2_get_cursor_plane()
4535 if (vop2->data->plane_table[i].plane_id == cursor_plane) { in rockchip_vop2_get_cursor_plane()
4536 plane_type = vop2->data->plane_table[i].plane_type; in rockchip_vop2_get_cursor_plane()
4542 for (i = 0; i < vop2->data->nr_layers; i++) { in rockchip_vop2_get_cursor_plane()
4543 if (vop2->data->plane_table[i].plane_type == plane_type && in rockchip_vop2_get_cursor_plane()
4544 vop2->data->plane_table[i].plane_id != cursor_plane) { in rockchip_vop2_get_cursor_plane()
4545 correct_cursor_plane = vop2->data->plane_table[i].plane_id; in rockchip_vop2_get_cursor_plane()
4565 struct vop2 *vop2 = cstate->private; in rockchip_vop2_fixup_dts() local
4574 if (vop_fix_dts || vop2->version == VOP_VERSION_RK3528) in rockchip_vop2_fixup_dts()
4579 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; in rockchip_vop2_fixup_dts()
4587 vop2->vp_plane_mask[vp_id].primary_plane_id, in rockchip_vop2_fixup_dts()
4593 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); in rockchip_vop2_fixup_dts()
4647 struct vop2 *vop2 = cstate->private; in rockchip_vop2_mode_fixup() local
4660 if (vop2->version == VOP_VERSION_RK3528 && conn_state->output_if & VOP_OUTPUT_IF_BT656) in rockchip_vop2_mode_fixup()
4694 struct vop2 *vop2 = cstate->private; in rockchip_vop2_plane_check() local
4700 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
4702 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); in rockchip_vop2_plane_check()
4725 struct vop2 *vop2 = cstate->private; in rockchip_vop2_apply_soft_te() local
4730 ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val, in rockchip_vop2_apply_soft_te()
4740 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_apply_soft_te()
4763 struct vop2 *vop2 = cstate->private; in rockchip_vop2_regs_dump() local
4764 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_regs_dump()
4777 printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4, in rockchip_vop2_regs_dump()
4778 vop2_readl(vop2, base + (4 * j)), in rockchip_vop2_regs_dump()
4779 vop2_readl(vop2, base + (4 * (j + 1))), in rockchip_vop2_regs_dump()
4780 vop2_readl(vop2, base + (4 * (j + 2))), in rockchip_vop2_regs_dump()
4781 vop2_readl(vop2, base + (4 * (j + 3)))); in rockchip_vop2_regs_dump()
4792 struct vop2 *vop2 = cstate->private; in rockchip_vop2_active_regs_dump() local
4793 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_active_regs_dump()
4805 enable_state = (vop2_readl(vop2, regs[i].state_base) >> regs[i].state_shift) & in rockchip_vop2_active_regs_dump()
4814 printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4, in rockchip_vop2_active_regs_dump()
4815 vop2_readl(vop2, base + (4 * j)), in rockchip_vop2_active_regs_dump()
4816 vop2_readl(vop2, base + (4 * (j + 1))), in rockchip_vop2_active_regs_dump()
4817 vop2_readl(vop2, base + (4 * (j + 2))), in rockchip_vop2_active_regs_dump()
4818 vop2_readl(vop2, base + (4 * (j + 3)))); in rockchip_vop2_active_regs_dump()