Lines Matching refs:cstate
1664 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_gamma_lut_init() local
1685 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); in rockchip_vop2_gamma_lut_init()
1709 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1712 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1713 if (cstate->splice_mode) { in rockchip_vop2_gamma_lut_init()
1714 rk3588_vop2_load_lut(vop2, cstate->splice_crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1727 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_cubic_lut_init() local
1729 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init()
1740 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); in rockchip_vop2_cubic_lut_init()
1765 get_cubic_lut_buffer(cstate->crtc_id)); in rockchip_vop2_cubic_lut_init()
1779 struct crtc_state *cstate = &state->crtc_state; in vop2_bcsh_reg_update() local
1783 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); in vop2_bcsh_reg_update()
1785 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); in vop2_bcsh_reg_update()
1788 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); in vop2_bcsh_reg_update()
1790 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); in vop2_bcsh_reg_update()
1792 if (!cstate->bcsh_en) { in vop2_bcsh_reg_update()
1821 struct crtc_state *cstate = &state->crtc_state; in vop2_tv_config_update() local
1834 cstate->bcsh_en = true; in vop2_tv_config_update()
1836 if (cstate->bcsh_en) { in vop2_tv_config_update()
1837 if (!cstate->yuv_overlay) in vop2_tv_config_update()
1838 cstate->post_r2y_en = 1; in vop2_tv_config_update()
1840 cstate->post_y2r_en = 1; in vop2_tv_config_update()
1842 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) in vop2_tv_config_update()
1843 cstate->post_r2y_en = 1; in vop2_tv_config_update()
1844 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) in vop2_tv_config_update()
1845 cstate->post_y2r_en = 1; in vop2_tv_config_update()
1848 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH); in vop2_tv_config_update()
1850 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) in vop2_tv_config_update()
1878 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
1879 if (cstate->splice_mode) in vop2_tv_config_update()
1880 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); in vop2_tv_config_update()
1887 struct crtc_state *cstate = &state->crtc_state; in vop2_setup_dly_for_vp() local
1892 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; in vop2_setup_dly_for_vp()
1896 if (cstate->splice_mode) in vop2_setup_dly_for_vp()
1913 struct crtc_state *cstate = &state->crtc_state; in vop3_setup_pipe_dly() local
1918 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in vop3_setup_pipe_dly()
1940 struct crtc_state *cstate = &state->crtc_state; in vop2_post_config() local
1941 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config()
1987 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
1989 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
1990 if (cstate->splice_mode) in vop2_post_config()
1991 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); in vop2_post_config()
1998 struct crtc_state *cstate = &state->crtc_state; in vop3_post_acm_config() local
2001 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config()
2060 struct crtc_state *cstate = &state->crtc_state; in vop3_post_csc_config() local
2068 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config()
2075 if (!cstate->yuv_overlay) in vop3_post_csc_config()
2082 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) in vop3_post_csc_config()
2086 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) in vop3_post_csc_config()
2093 if (cstate->yuv_overlay || post_r2y_en) in vop3_post_csc_config()
2099 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_13BIT_DEPTH); in vop3_post_csc_config()
2102 rockchip_calc_post_csc(csc, &csc_coef, cstate->post_csc_mode, is_input_yuv, in vop3_post_csc_config()
2135 POST_R2Y_MODE_MASK, POST_R2Y_MODE_SHIFT, cstate->post_csc_mode, false); in vop3_post_csc_config()
2280 struct crtc_state *cstate = &state->crtc_state; in vop2_overlay_init() local
2330 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; in vop2_overlay_init()
2372 struct crtc_state *cstate = &state->crtc_state; in vop2_global_initial() local
2387 if (cstate->crtc->assign_plane) {/* dts assign plane */ in vop2_global_initial()
2392 plane_mask = cstate->crtc->vps[i].plane_mask; in vop2_global_initial()
2396 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; in vop2_global_initial()
2414 if (cstate->crtc->vps[i].enable) in vop2_global_initial()
2428 cstate->crtc->vps[1].output_type == DRM_MODE_CONNECTOR_TV) in vop2_global_initial()
2439 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { in vop2_global_initial()
2457 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ in vop2_global_initial()
2507 ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode); in vop2_global_initial()
2539 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_preinit() local
2540 const struct vop2_data *vop2_data = cstate->crtc->data; in rockchip_vop2_preinit()
2552 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); in rockchip_vop2_preinit()
2565 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); in rockchip_vop2_preinit()
2575 cstate->private = rockchip_vop2; in rockchip_vop2_preinit()
2576 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; in rockchip_vop2_preinit()
2577 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; in rockchip_vop2_preinit()
2611 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_cru_cfg() local
2614 struct vop2 *vop2 = cstate->private; in vop2_calc_cru_cfg()
2645 if (cstate->dsc_enable) { in vop2_calc_cru_cfg()
2646 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; in vop2_calc_cru_cfg()
2647 if_dclk_rate = cstate->dsc_cds_clk_rate; in vop2_calc_cru_cfg()
2655 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2659 vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate); in vop2_calc_cru_cfg()
2680 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2683 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate); in vop2_calc_cru_cfg()
2691 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
2693 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; in vop2_calc_cru_cfg()
2700 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2703 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate); in vop2_calc_cru_cfg()
2707 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
2708 dclk_rate /= cstate->dsc_slice_num; in vop2_calc_cru_cfg()
2713 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
2733 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_dsc_clk() local
2740 cstate->dsc_txp_clk_rate = v_pixclk; in vop2_calc_dsc_clk()
2741 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); in vop2_calc_dsc_clk()
2743 cstate->dsc_pxl_clk_rate = v_pixclk; in vop2_calc_dsc_clk()
2744 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); in vop2_calc_dsc_clk()
2753 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); in vop2_calc_dsc_clk()
2760 struct crtc_state *cstate = &state->crtc_state; in rk3588_vop2_if_cfg() local
2763 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; in rk3588_vop2_if_cfg()
2764 struct vop2 *vop2 = cstate->private; in rk3588_vop2_if_cfg()
2765 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg()
2781 if (cstate->dsc_enable) { in rk3588_vop2_if_cfg()
2792 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; in rk3588_vop2_if_cfg()
2793 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; in rk3588_vop2_if_cfg()
2794 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; in rk3588_vop2_if_cfg()
2798 cstate->dsc_id, dsc_sink_cap->slice_width, in rk3588_vop2_if_cfg()
2799 dsc_sink_cap->slice_height, cstate->dsc_slice_num); in rk3588_vop2_if_cfg()
2802 …dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div… in rk3588_vop2_if_cfg()
2820 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
2837 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
2844 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
2846 else if (cstate->crtc_id == 3) in rk3588_vop2_if_cfg()
2863 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
2902 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2917 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2932 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2950 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2968 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2977 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2983 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); in rk3588_vop2_if_cfg()
2985 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); in rk3588_vop2_if_cfg()
2992 struct crtc_state *cstate = &state->crtc_state; in rk3568_vop2_if_cfg() local
2995 struct vop2 *vop2 = cstate->private; in rk3568_vop2_if_cfg()
2996 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_if_cfg()
3008 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3021 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3030 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3039 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3050 LVDS1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3076 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3085 MIPI1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3104 EDP0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3115 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3128 struct crtc_state *cstate = &state->crtc_state; in rk3528_vop2_if_cfg() local
3131 struct vop2 *vop2 = cstate->private; in rk3528_vop2_if_cfg()
3141 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
3148 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
3161 struct crtc_state *cstate = &state->crtc_state; in rk3562_vop2_if_cfg() local
3164 struct vop2 *vop2 = cstate->private; in rk3562_vop2_if_cfg()
3176 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3187 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3198 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3210 struct crtc_state *cstate = &state->crtc_state; in vop2_post_color_swap() local
3212 struct vop2 *vop2 = cstate->private; in vop2_post_color_swap()
3213 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap()
3259 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_dsc_cru_cfg() local
3261 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; in vop2_calc_dsc_cru_cfg()
3262 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; in vop2_calc_dsc_cru_cfg()
3263 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; in vop2_calc_dsc_cru_cfg()
3272 struct crtc_state *cstate = &state->crtc_state; in vop2_load_pps() local
3273 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; in vop2_load_pps()
3306 struct crtc_state *cstate = &state->crtc_state; in vop2_dsc_enable() local
3307 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; in vop2_dsc_enable()
3333 if (cstate->dsc_slice_num > dsc_data->max_slice_num) in vop2_dsc_enable()
3335 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); in vop2_dsc_enable()
3345 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); in vop2_dsc_enable()
3368 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); in vop2_dsc_enable()
3383 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; in vop2_dsc_enable()
3419 int delay_line_num = dsc_buf_size / cstate->dsc_slice_num / in vop2_dsc_enable()
3420 be16_to_cpu(cstate->pps.chunk_size); in vop2_dsc_enable()
3444 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / in vop2_dsc_enable()
3466 val |= DSC_CTRL0_DEF_CON | (ilog2(cstate->dsc_slice_num) << DSC_NSLC_SHIFT) | in vop2_dsc_enable()
3477 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, in vop2_dsc_enable()
3478 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, in vop2_dsc_enable()
3479 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); in vop2_dsc_enable()
3484 struct crtc_state *cstate = &state->crtc_state; in is_extend_pll() local
3485 struct vop2 *vop2 = cstate->private; in is_extend_pll()
3494 sprintf(vp_name, "port@%d", cstate->crtc_id); in is_extend_pll()
3524 struct crtc_state *cstate = &state->crtc_state; in vop3_mcu_mode_setup() local
3525 struct vop2 *vop2 = cstate->private; in vop3_mcu_mode_setup()
3526 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup()
3533 MCU_PIX_TOTAL_SHIFT, cstate->mcu_timing.mcu_pix_total, false); in vop3_mcu_mode_setup()
3535 MCU_CS_PST_SHIFT, cstate->mcu_timing.mcu_cs_pst, false); in vop3_mcu_mode_setup()
3537 MCU_CS_PEND_SHIFT, cstate->mcu_timing.mcu_cs_pend, false); in vop3_mcu_mode_setup()
3539 MCU_RW_PST_SHIFT, cstate->mcu_timing.mcu_rw_pst, false); in vop3_mcu_mode_setup()
3541 MCU_RW_PEND_SHIFT, cstate->mcu_timing.mcu_rw_pend, false); in vop3_mcu_mode_setup()
3546 struct crtc_state *cstate = &state->crtc_state; in vop3_mcu_bypass_mode_setup() local
3547 struct vop2 *vop2 = cstate->private; in vop3_mcu_bypass_mode_setup()
3548 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup()
3568 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_send_mcu_cmd() local
3571 struct vop2 *vop2 = cstate->private; in rockchip_vop2_send_mcu_cmd()
3572 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd()
3573 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_send_mcu_cmd()
3590 vop2_clk_set_rate(&cstate->dclk, 150000000); in rockchip_vop2_send_mcu_cmd()
3631 vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000); in rockchip_vop2_send_mcu_cmd()
3639 struct crtc_state *cstate = &state->crtc_state; in vop2_get_vrefresh() local
3643 if (cstate->mcu_timing.mcu_pix_total) in vop2_get_vrefresh()
3644 return mode->vrefresh / cstate->mcu_timing.mcu_pix_total; in vop2_get_vrefresh()
3651 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_init() local
3652 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_init()
3655 struct vop2 *vop2 = cstate->private; in rockchip_vop2_init()
3667 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init()
3668 u32 line_flag_offset = (cstate->crtc_id * 4); in rockchip_vop2_init()
3690 cstate->crtc_id); in rockchip_vop2_init()
3693 cstate->splice_mode = true; in rockchip_vop2_init()
3694 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
3695 if (!cstate->splice_crtc_id) { in rockchip_vop2_init()
3697 __func__, cstate->crtc_id); in rockchip_vop2_init()
3706 RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
3708 RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
3721 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) in rockchip_vop2_init()
3774 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
3777 cstate->yuv_overlay = yuv_overlay; in rockchip_vop2_init()
3831 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); in rockchip_vop2_init()
3838 if (cstate->splice_mode) { in rockchip_vop2_init()
3840 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, in rockchip_vop2_init()
3842 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); in rockchip_vop2_init()
3854 if (cstate->feature & (VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC)) in rockchip_vop2_init()
3857 if (cstate->dsc_enable) { in rockchip_vop2_init()
3862 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL); in rockchip_vop2_init()
3867 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_init()
3868 ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk); in rockchip_vop2_init()
3892 ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents", in rockchip_vop2_init()
3907 vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll); in rockchip_vop2_init()
3909 vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll); in rockchip_vop2_init()
3926 ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000); in rockchip_vop2_init()
3943 ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000); in rockchip_vop2_init()
3948 __func__, cstate->crtc_id, dclk_rate, ret); in rockchip_vop2_init()
3957 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); in rockchip_vop2_init()
3965 if (cstate->mcu_timing.mcu_pix_total) in rockchip_vop2_init()
4148 struct crtc_state *cstate = &state->crtc_state; in vop2_set_cluster_win() local
4151 struct vop2 *vop2 = cstate->private; in vop2_set_cluster_win()
4152 int src_w = cstate->src_rect.w; in vop2_set_cluster_win()
4153 int src_h = cstate->src_rect.h; in vop2_set_cluster_win()
4154 int crtc_x = cstate->crtc_rect.x; in vop2_set_cluster_win()
4155 int crtc_y = cstate->crtc_rect.y; in vop2_set_cluster_win()
4156 int crtc_w = cstate->crtc_rect.w; in vop2_set_cluster_win()
4157 int crtc_h = cstate->crtc_rect.h; in vop2_set_cluster_win()
4158 int xvir = cstate->xvir; in vop2_set_cluster_win()
4166 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in vop2_set_cluster_win()
4170 src_w = cstate->right_src_rect.w; in vop2_set_cluster_win()
4171 src_h = cstate->right_src_rect.h; in vop2_set_cluster_win()
4172 crtc_x = cstate->right_crtc_rect.x; in vop2_set_cluster_win()
4173 crtc_y = cstate->right_crtc_rect.y; in vop2_set_cluster_win()
4174 crtc_w = cstate->right_crtc_rect.w; in vop2_set_cluster_win()
4175 crtc_h = cstate->right_crtc_rect.h; in vop2_set_cluster_win()
4176 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; in vop2_set_cluster_win()
4178 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in vop2_set_cluster_win()
4211 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, in vop2_set_cluster_win()
4215 cstate->dma_addr + splice_yrgb_offset); in vop2_set_cluster_win()
4230 dither_up = vop2_win_dither_up(cstate->format); in vop2_set_cluster_win()
4241 struct crtc_state *cstate = &state->crtc_state; in vop2_set_smart_win() local
4244 struct vop2 *vop2 = cstate->private; in vop2_set_smart_win()
4245 int src_w = cstate->src_rect.w; in vop2_set_smart_win()
4246 int src_h = cstate->src_rect.h; in vop2_set_smart_win()
4247 int crtc_x = cstate->crtc_rect.x; in vop2_set_smart_win()
4248 int crtc_y = cstate->crtc_rect.y; in vop2_set_smart_win()
4249 int crtc_w = cstate->crtc_rect.w; in vop2_set_smart_win()
4250 int crtc_h = cstate->crtc_rect.h; in vop2_set_smart_win()
4251 int xvir = cstate->xvir; in vop2_set_smart_win()
4259 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in vop2_set_smart_win()
4263 src_w = cstate->right_src_rect.w; in vop2_set_smart_win()
4264 src_h = cstate->right_src_rect.h; in vop2_set_smart_win()
4265 crtc_x = cstate->right_crtc_rect.x; in vop2_set_smart_win()
4266 crtc_y = cstate->right_crtc_rect.y; in vop2_set_smart_win()
4267 crtc_w = cstate->right_crtc_rect.w; in vop2_set_smart_win()
4268 crtc_h = cstate->right_crtc_rect.h; in vop2_set_smart_win()
4269 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; in vop2_set_smart_win()
4271 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in vop2_set_smart_win()
4279 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); in vop2_set_smart_win()
4309 cstate->dma_addr += (src_h - 1) * xvir * 4; in vop2_set_smart_win()
4314 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, in vop2_set_smart_win()
4318 cstate->dma_addr + splice_yrgb_offset); in vop2_set_smart_win()
4336 dither_up = vop2_win_dither_up(cstate->format); in vop2_set_smart_win()
4345 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_display_rect_for_splice() local
4348 struct display_rect *src_rect = &cstate->src_rect; in vop2_calc_display_rect_for_splice()
4349 struct display_rect *dst_rect = &cstate->crtc_rect; in vop2_calc_display_rect_for_splice()
4382 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
4383 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
4384 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
4385 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
4390 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_set_plane() local
4391 struct vop2 *vop2 = cstate->private; in rockchip_vop2_set_plane()
4394 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
4397 if (cstate->crtc_rect.w > cstate->max_output.width) { in rockchip_vop2_set_plane()
4399 cstate->crtc_rect.w, cstate->max_output.width); in rockchip_vop2_set_plane()
4415 printf("open vp%d plane pd fail\n", cstate->crtc_id); in rockchip_vop2_set_plane()
4418 if (cstate->splice_mode) { in rockchip_vop2_set_plane()
4424 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); in rockchip_vop2_set_plane()
4444 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), in rockchip_vop2_set_plane()
4445 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, in rockchip_vop2_set_plane()
4446 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, in rockchip_vop2_set_plane()
4447 cstate->dma_addr); in rockchip_vop2_set_plane()
4460 struct crtc_state *cstate = &state->crtc_state; in vop2_dsc_cfg_done() local
4461 struct vop2 *vop2 = cstate->private; in vop2_dsc_cfg_done()
4462 u8 dsc_id = cstate->dsc_id; in vop2_dsc_cfg_done()
4478 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_enable() local
4479 struct vop2 *vop2 = cstate->private; in rockchip_vop2_enable()
4480 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable()
4481 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_enable()
4486 if (cstate->splice_mode) in rockchip_vop2_enable()
4487 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in rockchip_vop2_enable()
4491 if (cstate->dsc_enable) in rockchip_vop2_enable()
4494 if (cstate->mcu_timing.mcu_pix_total) in rockchip_vop2_enable()
4503 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_disable() local
4504 struct vop2 *vop2 = cstate->private; in rockchip_vop2_disable()
4505 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable()
4506 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_disable()
4511 if (cstate->splice_mode) in rockchip_vop2_disable()
4512 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in rockchip_vop2_disable()
4521 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_get_cursor_plane() local
4522 struct vop2 *vop2 = cstate->private; in rockchip_vop2_get_cursor_plane()
4557 cstate->crtc_id, cursor_plane, correct_cursor_plane); in rockchip_vop2_get_cursor_plane()
4564 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_fixup_dts() local
4565 struct vop2 *vop2 = cstate->private; in rockchip_vop2_fixup_dts()
4567 struct device_node *port_parent_node = cstate->ports_node; in rockchip_vop2_fixup_dts()
4581 if (cstate->crtc->assign_plane) in rockchip_vop2_fixup_dts()
4584 cstate->crtc->vps[vp_id].cursor_plane); in rockchip_vop2_fixup_dts()
4607 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_check() local
4608 struct rockchip_crtc *crtc = cstate->crtc; in rockchip_vop2_check()
4610 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { in rockchip_vop2_check()
4611 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); in rockchip_vop2_check()
4615 if (cstate->splice_mode) { in rockchip_vop2_check()
4617 crtc->splice_crtc_id = cstate->splice_crtc_id; in rockchip_vop2_check()
4626 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_mode_valid() local
4635 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); in rockchip_vop2_mode_valid()
4646 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_mode_fixup() local
4647 struct vop2 *vop2 = cstate->private; in rockchip_vop2_mode_fixup()
4663 if (cstate->mcu_timing.mcu_pix_total) { in rockchip_vop2_mode_fixup()
4693 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_plane_check() local
4694 struct vop2 *vop2 = cstate->private; in rockchip_vop2_plane_check()
4695 struct display_rect *src = &cstate->src_rect; in rockchip_vop2_plane_check()
4696 struct display_rect *dst = &cstate->crtc_rect; in rockchip_vop2_plane_check()
4700 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
4714 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); in rockchip_vop2_plane_check()
4724 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_apply_soft_te() local
4725 struct vop2 *vop2 = cstate->private; in rockchip_vop2_apply_soft_te()
4726 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te()
4744 cstate->crtc_id); in rockchip_vop2_apply_soft_te()
4748 printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
4753 printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
4762 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_regs_dump() local
4763 struct vop2 *vop2 = cstate->private; in rockchip_vop2_regs_dump()
4769 if (!cstate->crtc->active) in rockchip_vop2_regs_dump()
4791 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_active_regs_dump() local
4792 struct vop2 *vop2 = cstate->private; in rockchip_vop2_active_regs_dump()
4799 if (!cstate->crtc->active) in rockchip_vop2_active_regs_dump()