Lines Matching refs:crtc_id
1624 static void rk3568_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3568_vop2_load_lut() argument
1627 u32 vp_offset = crtc_id * 0x100; in rk3568_vop2_load_lut()
1632 crtc_id, false); in rk3568_vop2_load_lut()
1641 static void rk3588_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3588_vop2_load_lut() argument
1644 u32 vp_offset = crtc_id * 0x100; in rk3588_vop2_load_lut()
1649 crtc_id, false); in rk3588_vop2_load_lut()
1709 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1712 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1729 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init()
1740 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); in rockchip_vop2_cubic_lut_init()
1765 get_cubic_lut_buffer(cstate->crtc_id)); in rockchip_vop2_cubic_lut_init()
1777 struct bcsh_state *bcsh_state, int crtc_id) in vop2_bcsh_reg_update() argument
1780 u32 vp_offset = crtc_id * 0x100; in vop2_bcsh_reg_update()
1878 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
1883 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop2_setup_dly_for_vp() argument
1892 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; in vop2_setup_dly_for_vp()
1893 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; in vop2_setup_dly_for_vp()
1904 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, in vop2_setup_dly_for_vp()
1906 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop2_setup_dly_for_vp()
1909 static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop3_setup_pipe_dly() argument
1918 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in vop3_setup_pipe_dly()
1926 bg_dly = vop2->data->vp_data[crtc_id].win_dly + in vop3_setup_pipe_dly()
1927 vop2->data->vp_data[crtc_id].layer_mix_dly + in vop3_setup_pipe_dly()
1928 vop2->data->vp_data[crtc_id].hdr_mix_dly; in vop3_setup_pipe_dly()
1931 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
1933 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop3_setup_pipe_dly()
1941 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config()
1987 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
1989 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
2001 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config()
2068 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config()
2576 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; in rockchip_vop2_preinit()
2577 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; in rockchip_vop2_preinit()
2655 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2659 vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate); in vop2_calc_cru_cfg()
2680 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2683 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate); in vop2_calc_cru_cfg()
2700 vop2->data->vp_data[cstate->crtc_id].max_dclk); in vop2_calc_cru_cfg()
2703 vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate); in vop2_calc_cru_cfg()
2765 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg()
2820 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
2844 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
2846 else if (cstate->crtc_id == 3) in rk3588_vop2_if_cfg()
2902 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2917 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2932 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2950 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2968 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2977 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
2996 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_if_cfg()
3008 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3021 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3030 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3039 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3050 LVDS1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3076 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3085 MIPI1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3104 EDP0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3115 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
3141 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
3148 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
3176 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3187 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3198 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
3213 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap()
3345 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); in vop2_dsc_enable()
3494 sprintf(vp_name, "port@%d", cstate->crtc_id); in is_extend_pll()
3526 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup()
3548 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup()
3572 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd()
3573 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_send_mcu_cmd()
3652 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_init()
3667 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init()
3668 u32 line_flag_offset = (cstate->crtc_id * 4); in rockchip_vop2_init()
3690 cstate->crtc_id); in rockchip_vop2_init()
3694 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
3697 __func__, cstate->crtc_id); in rockchip_vop2_init()
3706 RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
3708 RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
3774 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
3831 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); in rockchip_vop2_init()
3867 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_init()
3948 __func__, cstate->crtc_id, dclk_rate, ret); in rockchip_vop2_init()
3957 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); in rockchip_vop2_init()
4166 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in vop2_set_cluster_win()
4259 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in vop2_set_smart_win()
4279 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); in vop2_set_smart_win()
4394 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
4415 printf("open vp%d plane pd fail\n", cstate->crtc_id); in rockchip_vop2_set_plane()
4444 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), in rockchip_vop2_set_plane()
4480 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable()
4481 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_enable()
4505 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable()
4506 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_disable()
4557 cstate->crtc_id, cursor_plane, correct_cursor_plane); in rockchip_vop2_get_cursor_plane()
4610 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { in rockchip_vop2_check()
4611 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); in rockchip_vop2_check()
4635 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); in rockchip_vop2_mode_valid()
4700 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
4714 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); in rockchip_vop2_plane_check()
4726 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te()
4744 cstate->crtc_id); in rockchip_vop2_apply_soft_te()
4748 printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
4753 printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()