Lines Matching refs:crtc_clock
2615 unsigned long v_pixclk = mode->crtc_clock; in vop2_calc_cru_cfg()
2734 u64 v_pixclk = mode->crtc_clock * 1000LL; /* video timing pixclk */ in vop2_calc_dsc_clk()
3156 return mode->crtc_clock; in rk3528_vop2_if_cfg()
3205 return mode->crtc_clock; in rk3562_vop2_if_cfg()
3384 u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */ in vop2_dsc_enable()
3631 vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000); in rockchip_vop2_send_mcu_cmd()
3905 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) { in rockchip_vop2_init()
3954 mode->crtc_clock = ret / 4 / 1000; in rockchip_vop2_init()
3956 mode->crtc_clock = ret * dclk_div_factor / 1000; in rockchip_vop2_init()
3957 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); in rockchip_vop2_init()
4652 mode->crtc_clock *= 2; in rockchip_vop2_mode_fixup()
4661 mode->crtc_clock *= 4; in rockchip_vop2_mode_fixup()
4669 mode->crtc_clock *= 3; in rockchip_vop2_mode_fixup()
4675 mode->crtc_clock *= 4; in rockchip_vop2_mode_fixup()
4679 mode->crtc_clock *= 2; in rockchip_vop2_mode_fixup()