44 #define EN_MASK					1  macro
1638 			EN_MASK, DSP_LUT_EN_SHIFT, 1, false);  in rk3568_vop2_load_lut()
1655 			EN_MASK, DSP_LUT_EN_SHIFT, 1, false);  in rk3588_vop2_load_lut()
1657 			EN_MASK, GAMMA_UPDATE_EN_SHIFT, 1, false);  in rk3588_vop2_load_lut()
1767 			EN_MASK, LUT_DMA_EN_SHIFT, 1, false);  in rockchip_vop2_cubic_lut_init()
1769 			EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false);  in rockchip_vop2_cubic_lut_init()
1771 			EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false);  in rockchip_vop2_cubic_lut_init()
2181 	is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift);  in vop2_wait_power_domain_on()
2217 	vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK,  in vop2_power_domain_on()
2384 		vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,  in vop2_global_initial()
2477 	vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,  in vop2_global_initial()
2479 	vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in vop2_global_initial()
2515 		vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK,  in vop2_global_initial()
2826 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2829 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT,  in rk3588_vop2_if_cfg()
2837 					EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);  in rk3588_vop2_if_cfg()
2839 					EN_MASK, EDPI_WMS_HOLD_EN, 1, false);  in rk3588_vop2_if_cfg()
2851 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2854 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT,  in rk3588_vop2_if_cfg()
2863 					EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);  in rk3588_vop2_if_cfg()
2865 					EN_MASK, EDPI_WMS_HOLD_EN, 1, false);  in rk3588_vop2_if_cfg()
2870 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3588_vop2_if_cfg()
2874 					EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1,  in rk3588_vop2_if_cfg()
2878 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2882 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2886 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2890 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3588_vop2_if_cfg()
2899 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT,  in rk3588_vop2_if_cfg()
2909 		vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK,  in rk3588_vop2_if_cfg()
2914 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT,  in rk3588_vop2_if_cfg()
2924 		vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK,  in rk3588_vop2_if_cfg()
2929 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT,  in rk3588_vop2_if_cfg()
2939 		vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK,  in rk3588_vop2_if_cfg()
2947 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT,  in rk3588_vop2_if_cfg()
2957 		vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK,  in rk3588_vop2_if_cfg()
2965 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT,  in rk3588_vop2_if_cfg()
2974 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT,  in rk3588_vop2_if_cfg()
3005 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3568_vop2_if_cfg()
3011 		vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,  in rk3568_vop2_if_cfg()
3016 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3568_vop2_if_cfg()
3018 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK,  in rk3568_vop2_if_cfg()
3022 		vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,  in rk3568_vop2_if_cfg()
3027 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,  in rk3568_vop2_if_cfg()
3031 		vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,  in rk3568_vop2_if_cfg()
3036 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,  in rk3568_vop2_if_cfg()
3042 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3047 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT,  in rk3568_vop2_if_cfg()
3053 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3060 		vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3568_vop2_if_cfg()
3064 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3568_vop2_if_cfg()
3068 			vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK,  in rk3568_vop2_if_cfg()
3073 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,  in rk3568_vop2_if_cfg()
3077 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3082 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT,  in rk3568_vop2_if_cfg()
3086 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3092 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3568_vop2_if_cfg()
3096 					EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1,  in rk3568_vop2_if_cfg()
3101 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT,  in rk3568_vop2_if_cfg()
3105 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3112 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,  in rk3568_vop2_if_cfg()
3116 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3568_vop2_if_cfg()
3138 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,  in rk3528_vop2_if_cfg()
3145 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,  in rk3528_vop2_if_cfg()
3149 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3528_vop2_if_cfg()
3173 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3562_vop2_if_cfg()
3177 		vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK,  in rk3562_vop2_if_cfg()
3184 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,  in rk3562_vop2_if_cfg()
3188 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3562_vop2_if_cfg()
3195 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,  in rk3562_vop2_if_cfg()
3199 		vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,  in rk3562_vop2_if_cfg()
3342 	vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK,  in vop2_dsc_enable()
3375 	vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK,  in vop2_dsc_enable()
3528 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_mode_setup()
3530 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_mode_setup()
3550 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_bypass_mode_setup()
3552 	vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in vop3_mcu_bypass_mode_setup()
3582 		vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3584 		vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3587 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3595 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3600 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3604 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3611 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3624 		vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3626 		vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3629 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_send_mcu_cmd()
3701 		vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK,  in rockchip_vop2_init()
3705 	vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,  in rockchip_vop2_init()
3707 	vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,  in rockchip_vop2_init()
3764 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3766 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3768 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3770 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3774 	vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id,  in rockchip_vop2_init()
3797 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3799 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3801 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3806 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3808 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3817 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3820 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3845 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
3849 		vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_init()
4043 					EN_MASK, CLUSTER_XGT_EN_SHIFT, xgt_en, false);  in vop2_setup_scale()
4045 					EN_MASK, CLUSTER_XAVG_EN_SHIFT, xavg_en, false);  in vop2_setup_scale()
4089 					EN_MASK, ESMART_XGT_EN_SHIFT, xgt_en, false);  in vop2_setup_scale()
4091 					EN_MASK, ESMART_XAVG_EN_SHIFT, xavg_en, false);  in vop2_setup_scale()
4208 				EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false);  in vop2_set_cluster_win()
4221 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
4224 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
4231 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
4234 	vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
4310 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK,  in vop2_set_smart_win()
4326 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()
4330 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,  in vop2_set_smart_win()
4337 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()
4466 		vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK,  in vop2_dsc_cfg_done()
4468 		vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK,  in vop2_dsc_cfg_done()
4471 		vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK,  in vop2_dsc_cfg_done()
4483 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_enable()
4495 		vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_enable()
4508 	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,  in rockchip_vop2_disable()
4741 						EN_MASK, EDPI_WMS_FS, 1, false);  in rockchip_vop2_apply_soft_te()