Lines Matching +full:0 +full:x1294
40 #define RK3568_REG_CFG_DONE 0x000
43 #define RK3568_VERSION_INFO 0x004
46 #define RK3568_AUTO_GATING_CTRL 0x008
50 #define RK3568_SYS_AXI_LUT_CTRL 0x024
51 #define LUT_DMA_EN_SHIFT 0
54 #define RK3568_DSP_IF_EN 0x028
55 #define RGB_EN_SHIFT 0
56 #define RK3588_DP0_EN_SHIFT 0
87 #define RK3568_DSP_IF_CTRL 0x02c
88 #define LVDS_DUAL_EN_SHIFT 0
101 #define RK3568_DSP_IF_POL 0x030
106 #define IF_CTRL_EDP_PIN_POL_MASK 0x7
109 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7
112 #define IF_CTRL_RGB_LVDS_PIN_POL_MASK 0x7
113 #define IF_CTRL_RGB_LVDS_PIN_POL_SHIFT 0
117 #define RK3562_IF_PIN_POL_MASK 0x7
121 #define RK3588_IF_PIN_POL_MASK 0x7
130 #define RK3568_SYS_OTP_WIN_EN 0x50
131 #define OTP_WIN_EN_SHIFT 0
132 #define RK3568_SYS_LUT_PORT_SEL 0x58
133 #define GAMMA_PORT_SEL_MASK 0x3
134 #define GAMMA_PORT_SEL_SHIFT 0
135 #define GAMMA_AHB_WRITE_SEL_MASK 0x3
138 #define ESMART_LB_MODE_SEL_MASK 0x3
141 #define RK3568_SYS_PD_CTRL 0x034
142 #define RK3568_VP0_LINE_FLAG 0x70
143 #define RK3568_VP1_LINE_FLAG 0x74
144 #define RK3568_VP2_LINE_FLAG 0x78
145 #define RK3568_SYS0_INT_EN 0x80
146 #define RK3568_SYS0_INT_CLR 0x84
147 #define RK3568_SYS0_INT_STATUS 0x88
148 #define RK3568_SYS1_INT_EN 0x90
149 #define RK3568_SYS1_INT_CLR 0x94
150 #define RK3568_SYS1_INT_STATUS 0x98
151 #define RK3568_VP0_INT_EN 0xA0
152 #define RK3568_VP0_INT_CLR 0xA4
153 #define RK3568_VP0_INT_STATUS 0xA8
154 #define RK3568_VP1_INT_EN 0xB0
155 #define RK3568_VP1_INT_CLR 0xB4
156 #define RK3568_VP1_INT_STATUS 0xB8
157 #define RK3568_VP2_INT_EN 0xC0
158 #define RK3568_VP2_INT_CLR 0xC4
159 #define RK3568_VP2_INT_STATUS 0xC8
160 #define RK3588_CLUSTER0_PD_EN_SHIFT 0
168 #define RK3588_SYS_VAR_FREQ_CTRL 0x038
173 #define RK3568_SYS_STATUS0 0x60
182 #define RK3568_SYS_CTRL_LINE_FLAG0 0x70
183 #define LINE_FLAG_NUM_MASK 0x1fff
184 #define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0
188 #define RK3588_DSC_8K_SYS_CTRL 0x200
189 #define DSC_PORT_SEL_MASK 0x3
190 #define DSC_PORT_SEL_SHIFT 0
191 #define DSC_MAN_MODE_MASK 0x1
193 #define DSC_INTERFACE_MODE_MASK 0x3
195 #define DSC_PIXEL_NUM_MASK 0x3
197 #define DSC_PXL_CLK_DIV_MASK 0x1
199 #define DSC_CDS_CLK_DIV_MASK 0x3
201 #define DSC_TXP_CLK_DIV_MASK 0x3
203 #define DSC_INIT_DLY_MODE_MASK 0x1
208 #define RK3588_DSC_8K_RST 0x204
209 #define RST_DEASSERT_MASK 0x1
210 #define RST_DEASSERT_SHIFT 0
212 #define RK3588_DSC_8K_CFG_DONE 0x208
213 #define DSC_CFG_DONE_SHIFT 0
215 #define RK3588_DSC_8K_INIT_DLY 0x20C
216 #define DSC_INIT_DLY_NUM_MASK 0xffff
217 #define DSC_INIT_DLY_NUM_SHIFT 0
220 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210
221 #define DSC_HTOTAL_PW_MASK 0xffffffff
222 #define DSC_HTOTAL_PW_SHIFT 0
224 #define RK3588_DSC_8K_HACT_ST_END 0x214
225 #define DSC_HACT_ST_END_MASK 0xffffffff
226 #define DSC_HACT_ST_END_SHIFT 0
228 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218
229 #define DSC_VTOTAL_PW_MASK 0xffffffff
230 #define DSC_VTOTAL_PW_SHIFT 0
232 #define RK3588_DSC_8K_VACT_ST_END 0x21C
233 #define DSC_VACT_ST_END_MASK 0xffffffff
234 #define DSC_VACT_ST_END_SHIFT 0
236 #define RK3588_DSC_8K_STATUS 0x220
239 #define RK3528_OVL_SYS 0x500
240 #define RK3528_OVL_SYS_PORT_SEL_IMD 0x504
241 #define RK3528_OVL_SYS_GATING_EN_IMD 0x508
242 #define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510
243 #define RK3528_OVL_SYS_ESMART0_CTRL 0x520
244 #define ESMART_DLY_NUM_MASK 0xff
245 #define ESMART_DLY_NUM_SHIFT 0
246 #define RK3528_OVL_SYS_ESMART1_CTRL 0x524
247 #define RK3528_OVL_SYS_ESMART2_CTRL 0x528
248 #define RK3528_OVL_SYS_ESMART3_CTRL 0x52C
249 #define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
250 #define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
251 #define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
252 #define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
254 #define RK3528_OVL_PORT0_CTRL 0x600
255 #define RK3568_OVL_CTRL 0x600
256 #define OVL_MODE_SEL_MASK 0x1
257 #define OVL_MODE_SEL_SHIFT 0
259 #define RK3528_OVL_PORT0_LAYER_SEL 0x604
260 #define RK3568_OVL_LAYER_SEL 0x604
261 #define LAYER_SEL_MASK 0xf
263 #define RK3568_OVL_PORT_SEL 0x608
264 #define PORT_MUX_MASK 0xf
265 #define PORT_MUX_SHIFT 0
266 #define LAYER_SEL_PORT_MASK 0x3
269 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
270 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
271 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
272 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
273 #define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
274 #define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624
275 #define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628
276 #define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C
277 #define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630
278 #define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634
279 #define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638
280 #define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C
281 #define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640
282 #define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
283 #define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
284 #define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
285 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
286 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
287 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
288 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
289 #define RK3528_HDR_SRC_COLOR_CTRL 0x660
290 #define RK3528_HDR_DST_COLOR_CTRL 0x664
291 #define RK3528_HDR_SRC_ALPHA_CTRL 0x668
292 #define RK3528_HDR_DST_ALPHA_CTRL 0x66C
293 #define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670
294 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
295 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
296 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
297 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
298 #define RK3568_VP0_BG_MIX_CTRL 0x6E0
299 #define BG_MIX_CTRL_MASK 0xff
301 #define RK3568_VP1_BG_MIX_CTRL 0x6E4
302 #define RK3568_VP2_BG_MIX_CTRL 0x6E8
303 #define RK3568_CLUSTER_DLY_NUM 0x6F0
304 #define RK3568_SMART_DLY_NUM 0x6F8
306 #define RK3528_OVL_PORT1_CTRL 0x700
307 #define RK3528_OVL_PORT1_LAYER_SEL 0x704
308 #define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720
309 #define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724
310 #define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728
311 #define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C
312 #define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730
313 #define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734
314 #define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738
315 #define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C
316 #define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740
317 #define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744
318 #define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
319 #define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
320 #define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
323 #define RK3568_VP0_DSP_CTRL 0xC00
324 #define OUT_MODE_MASK 0xf
325 #define OUT_MODE_SHIFT 0
326 #define DATA_SWAP_MASK 0x1f
328 #define DSP_BG_SWAP 0x1
329 #define DSP_RB_SWAP 0x2
330 #define DSP_RG_SWAP 0x4
331 #define DSP_DELTA_SWAP 0x8
346 #define RK3568_VP0_MIPI_CTRL 0xC04
348 #define DCLK_DIV2_MASK 0x3
356 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08
358 #define RK3568_VP0_DCLK_SEL 0xC0C
360 #define RK3568_VP0_3D_LUT_CTRL 0xC10
361 #define VP0_3D_LUT_EN_SHIFT 0
364 #define RK3588_VP0_CLK_CTRL 0xC0C
365 #define DCLK_CORE_DIV_SHIFT 0
368 #define RK3568_VP0_3D_LUT_MST 0xC20
370 #define RK3568_VP0_DSP_BG 0xC2C
371 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30
372 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34
373 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38
374 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C
375 #define RK3568_VP0_POST_SCL_CTRL 0xC40
376 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44
377 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48
378 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C
379 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50
380 #define RK3568_VP0_DSP_VACT_ST_END 0xC54
381 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58
382 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C
384 #define RK3568_VP0_BCSH_CTRL 0xC60
385 #define BCSH_CTRL_Y2R_SHIFT 0
386 #define BCSH_CTRL_Y2R_MASK 0x1
388 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3
390 #define BCSH_CTRL_R2Y_MASK 0x1
392 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3
394 #define RK3568_VP0_BCSH_BCS 0xC64
395 #define BCSH_BRIGHTNESS_SHIFT 0
396 #define BCSH_BRIGHTNESS_MASK 0xFF
398 #define BCSH_CONTRAST_MASK 0x1FF
400 #define BCSH_SATURATION_MASK 0x3FF
402 #define BCSH_OUT_MODE_MASK 0x3
404 #define RK3568_VP0_BCSH_H 0xC68
405 #define BCSH_SIN_HUE_SHIFT 0
406 #define BCSH_SIN_HUE_MASK 0x1FF
408 #define BCSH_COS_HUE_MASK 0x1FF
410 #define RK3568_VP0_BCSH_COLOR 0xC6C
414 #define RK3528_VP0_ACM_CTRL 0xCD0
415 #define POST_CSC_COE00_MASK 0xFFFF
417 #define POST_R2Y_MODE_MASK 0x7
419 #define POST_CSC_MODE_MASK 0x7
421 #define POST_R2Y_EN_MASK 0x1
423 #define POST_CSC_EN_MASK 0x1
425 #define POST_ACM_BYPASS_EN_MASK 0x1
426 #define POST_ACM_BYPASS_EN_SHIFT 0
427 #define RK3528_VP0_CSC_COE01_02 0xCD4
428 #define RK3528_VP0_CSC_COE10_11 0xCD8
429 #define RK3528_VP0_CSC_COE12_20 0xCDC
430 #define RK3528_VP0_CSC_COE21_22 0xCE0
431 #define RK3528_VP0_CSC_OFFSET0 0xCE4
432 #define RK3528_VP0_CSC_OFFSET1 0xCE8
433 #define RK3528_VP0_CSC_OFFSET2 0xCEC
435 #define RK3562_VP0_MCU_CTRL 0xCF8
442 #define MCU_CLK_SEL_MASK 0x1
444 #define MCU_RW_PEND_MASK 0x3F
446 #define MCU_RW_PST_MASK 0xF
448 #define MCU_CS_PEND_MASK 0x3F
450 #define MCU_CS_PST_MASK 0xF
451 #define MCU_PIX_TOTAL_SHIFT 0
452 #define MCU_PIX_TOTAL_MASK 0x3F
454 #define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC
455 #define MCU_WRITE_DATA_BYPASS_SHIFT 0
456 #define MCU_WRITE_DATA_BYPASS_MASK 0xFFFFFFFF
458 #define RK3568_VP1_DSP_CTRL 0xD00
459 #define RK3568_VP1_MIPI_CTRL 0xD04
460 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08
461 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30
462 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34
463 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38
464 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C
465 #define RK3568_VP1_POST_SCL_CTRL 0xD40
466 #define RK3568_VP1_DSP_HACT_INFO 0xD34
467 #define RK3568_VP1_DSP_VACT_INFO 0xD38
468 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44
469 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48
470 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C
471 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50
472 #define RK3568_VP1_DSP_VACT_ST_END 0xD54
473 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58
474 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C
476 #define RK3568_VP2_DSP_CTRL 0xE00
477 #define RK3568_VP2_MIPI_CTRL 0xE04
478 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08
479 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30
480 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34
481 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38
482 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C
483 #define RK3568_VP2_POST_SCL_CTRL 0xE40
484 #define RK3568_VP2_DSP_HACT_INFO 0xE34
485 #define RK3568_VP2_DSP_VACT_INFO 0xE38
486 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44
487 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48
488 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C
489 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50
490 #define RK3568_VP2_DSP_VACT_ST_END 0xE54
491 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58
492 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C
495 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000
500 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
504 #define AVG2_MASK 0x1
506 #define AVG4_MASK 0x1
510 #define XGT_MODE_MASK 0x3
515 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
516 #define CLUSTER_AXI_YRGB_ID_MASK 0x1f
517 #define CLUSTER_AXI_YRGB_ID_SHIFT 0
518 #define CLUSTER_AXI_UV_ID_MASK 0x1f
521 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010
522 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014
523 #define RK3568_CLUSTER0_WIN0_VIR 0x1018
524 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020
525 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024
526 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028
527 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030
528 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054
529 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058
530 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C
531 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060
532 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
533 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
534 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
537 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
538 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
539 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090
540 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094
541 #define RK3568_CLUSTER0_WIN1_VIR 0x1098
542 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0
543 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4
544 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8
545 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0
546 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4
547 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8
548 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC
549 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0
550 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4
551 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8
552 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC
554 #define RK3568_CLUSTER0_CTRL 0x1100
555 #define CLUSTER_EN_SHIFT 0
556 #define CLUSTER_AXI_ID_MASK 0x1
559 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200
560 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204
561 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210
562 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214
563 #define RK3568_CLUSTER1_WIN0_VIR 0x1218
564 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220
565 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224
566 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228
567 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230
568 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254
569 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258
570 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C
571 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260
572 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264
573 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268
574 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C
576 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280
577 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284
578 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290
579 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294
580 #define RK3568_CLUSTER1_WIN1_VIR 0x1298
581 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0
582 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4
583 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8
584 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0
585 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4
586 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8
587 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC
588 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0
589 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4
590 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8
591 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC
593 #define RK3568_CLUSTER1_CTRL 0x1300
596 #define RK3568_ESMART0_CTRL0 0x1800
599 #define CSC_MODE_MASK 0x3
601 #define ESMART_LB_SELECT_MASK 0x3
603 #define RK3568_ESMART0_CTRL1 0x1804
604 #define ESMART_AXI_YRGB_ID_MASK 0x1f
606 #define ESMART_AXI_UV_ID_MASK 0x1f
610 #define RK3568_ESMART0_AXI_CTRL 0x1808
611 #define ESMART_AXI_ID_MASK 0x1
614 #define RK3568_ESMART0_REGION0_CTRL 0x1810
615 #define WIN_EN_SHIFT 0
616 #define WIN_FORMAT_MASK 0x1f
624 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
625 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818
626 #define RK3568_ESMART0_REGION0_VIR 0x181C
627 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820
628 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824
629 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828
630 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830
631 #define YRGB_XSCL_MODE_MASK 0x3
632 #define YRGB_XSCL_MODE_SHIFT 0
633 #define YRGB_XSCL_FILTER_MODE_MASK 0x3
635 #define YRGB_YSCL_MODE_MASK 0x3
637 #define YRGB_YSCL_FILTER_MODE_MASK 0x3
640 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834
641 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838
642 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C
643 #define RK3568_ESMART0_REGION1_CTRL 0x1840
644 #define YRGB_GT2_MASK 0x1
646 #define YRGB_GT4_MASK 0x1
649 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844
650 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848
651 #define RK3568_ESMART0_REGION1_VIR 0x184C
652 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850
653 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854
654 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858
655 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860
656 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864
657 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868
658 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C
659 #define RK3568_ESMART0_REGION2_CTRL 0x1870
660 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874
661 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878
662 #define RK3568_ESMART0_REGION2_VIR 0x187C
663 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880
664 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884
665 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888
666 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890
667 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894
668 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898
669 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C
670 #define RK3568_ESMART0_REGION3_CTRL 0x18A0
671 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4
672 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8
673 #define RK3568_ESMART0_REGION3_VIR 0x18AC
674 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0
675 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4
676 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8
677 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0
678 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4
679 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8
680 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC
682 #define RK3568_ESMART1_CTRL0 0x1A00
683 #define RK3568_ESMART1_CTRL1 0x1A04
684 #define RK3568_ESMART1_REGION0_CTRL 0x1A10
685 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14
686 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18
687 #define RK3568_ESMART1_REGION0_VIR 0x1A1C
688 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20
689 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24
690 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28
691 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30
692 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34
693 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38
694 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C
695 #define RK3568_ESMART1_REGION1_CTRL 0x1A40
696 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44
697 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48
698 #define RK3568_ESMART1_REGION1_VIR 0x1A4C
699 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50
700 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54
701 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58
702 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60
703 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64
704 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68
705 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C
706 #define RK3568_ESMART1_REGION2_CTRL 0x1A70
707 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74
708 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78
709 #define RK3568_ESMART1_REGION2_VIR 0x1A7C
710 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80
711 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84
712 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88
713 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90
714 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94
715 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98
716 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C
717 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0
718 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4
719 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8
720 #define RK3568_ESMART1_REGION3_VIR 0x1AAC
721 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0
722 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4
723 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8
724 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0
725 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4
726 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8
727 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC
729 #define RK3568_SMART0_CTRL0 0x1C00
730 #define RK3568_SMART0_CTRL1 0x1C04
731 #define RK3568_SMART0_REGION0_CTRL 0x1C10
732 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14
733 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18
734 #define RK3568_SMART0_REGION0_VIR 0x1C1C
735 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20
736 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24
737 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28
738 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30
739 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34
740 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38
741 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C
742 #define RK3568_SMART0_REGION1_CTRL 0x1C40
743 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44
744 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48
745 #define RK3568_SMART0_REGION1_VIR 0x1C4C
746 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50
747 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54
748 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58
749 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60
750 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64
751 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68
752 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C
753 #define RK3568_SMART0_REGION2_CTRL 0x1C70
754 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74
755 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78
756 #define RK3568_SMART0_REGION2_VIR 0x1C7C
757 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80
758 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84
759 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88
760 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90
761 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94
762 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98
763 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C
764 #define RK3568_SMART0_REGION3_CTRL 0x1CA0
765 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4
766 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8
767 #define RK3568_SMART0_REGION3_VIR 0x1CAC
768 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0
769 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4
770 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8
771 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0
772 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4
773 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8
774 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC
776 #define RK3568_SMART1_CTRL0 0x1E00
777 #define RK3568_SMART1_CTRL1 0x1E04
778 #define RK3568_SMART1_REGION0_CTRL 0x1E10
779 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14
780 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18
781 #define RK3568_SMART1_REGION0_VIR 0x1E1C
782 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20
783 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24
784 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28
785 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30
786 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34
787 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38
788 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C
789 #define RK3568_SMART1_REGION1_CTRL 0x1E40
790 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44
791 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48
792 #define RK3568_SMART1_REGION1_VIR 0x1E4C
793 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50
794 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54
795 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58
796 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60
797 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64
798 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68
799 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C
800 #define RK3568_SMART1_REGION2_CTRL 0x1E70
801 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74
802 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78
803 #define RK3568_SMART1_REGION2_VIR 0x1E7C
804 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80
805 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84
806 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88
807 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90
808 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94
809 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98
810 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C
811 #define RK3568_SMART1_REGION3_CTRL 0x1EA0
812 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4
813 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8
814 #define RK3568_SMART1_REGION3_VIR 0x1EAC
815 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0
816 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4
817 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8
818 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0
819 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4
820 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
821 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
824 #define RK3568_HDR_LUT_CTRL 0x2000
826 #define RK3588_VP3_DSP_CTRL 0xF00
827 #define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
828 #define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
831 #define RK3588_DSC_8K_PPS0_3 0x4000
832 #define RK3588_DSC_8K_CTRL0 0x40A0
833 #define DSC_EN_SHIFT 0
840 #define DSC_NSLC_MASK 0x7
845 #define DSC_CTRL0_DEF_CON ((1 << DSC_EN_SHIFT) | (1 << DSC_RBIT_SHIFT) | (0 << DSC_RBYT_SHIFT) | \
846 (1 << DSC_FLAL_SHIFT) | (1 << DSC_MER_SHIFT) | (0 << DSC_EPB_SHIFT) | \
849 #define RK3588_DSC_8K_CTRL1 0x40A4
850 #define RK3588_DSC_8K_STS0 0x40A8
851 #define RK3588_DSC_8K_ERS 0x40C4
853 #define RK3588_DSC_4K_PPS0_3 0x4100
854 #define RK3588_DSC_4K_CTRL0 0x41A0
855 #define RK3588_DSC_4K_CTRL1 0x41A4
856 #define RK3588_DSC_4K_STS0 0x41A8
857 #define RK3588_DSC_4K_ERS 0x41C4
860 #define RK3528_HDR_LUT_CTRL 0x2000
863 #define RK3528_ACM_CTRL 0x6400
864 #define RK3528_ACM_DELTA_RANGE 0x6404
865 #define RK3528_ACM_FETCH_START 0x6408
866 #define RK3528_ACM_FETCH_DONE 0x6420
867 #define RK3528_ACM_YHS_DEL_HY_SEG0 0x6500
868 #define RK3528_ACM_YHS_DEL_HY_SEG152 0x6760
869 #define RK3528_ACM_YHS_DEL_HS_SEG0 0x6764
870 #define RK3528_ACM_YHS_DEL_HS_SEG220 0x6ad4
871 #define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x6ad8
872 #define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x6bd8
874 #define RK3568_MAX_REG 0x1ED0
876 #define RK3562_GRF_IOC_VO_IO_CON 0x10500
877 #define RK3568_GRF_VO_CON1 0x0364
882 #define RK3588_GRF_VOP_CON2 0x0008
883 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0
888 #define RK3588_GRF_VO1_CON0 0x0000
889 #define HDMI_SYNC_POL_MASK 0x3
893 #define RK3588_PMU_BISR_CON3 0x20C
902 #define RK3588_PMU_BISR_STATUS5 0x294
915 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
923 #define ROCKCHIP_VOP2_DSC_8K 0
928 * should be all none zero, 0 will be
931 #define VOP2_PD_CLUSTER0 BIT(0)
941 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
953 #define WIN_FEATURE_HDR2SDR BIT(0)
970 #define V4L2_COLORSPACE_BT709F 0xfe
971 #define V4L2_COLORSPACE_BT2020F 0xff
990 HSYNC_POSITIVE = 0,
1014 RGB888_TO_RGB565 = 0x0,
1015 RGB888_TO_RGB666 = 0x1
1027 CLUSTER_LAYER = 0,
1034 ROCKCHIP_VOP2_CLUSTER0 = 0,
1060 SCALE_NONE = 0x0,
1061 SCALE_UP = 0x1,
1062 SCALE_DOWN = 0x2
1066 VOP_DSC_IF_DISABLE = 0,
1254 uint32_t fac = 0; in vop2_scale_factor()
1255 int i = 0; in vop2_scale_factor()
1258 return 0; in vop2_scale_factor()
1270 for (i = 0; i < 100; i++) { in vop2_scale_factor()
1274 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); in vop2_scale_factor()
1278 for (i = 0; i < 100; i++) { in vop2_scale_factor()
1282 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); in vop2_scale_factor()
1299 uint32_t fac = 0; in vop3_scale_factor()
1300 int i = 0; in vop3_scale_factor()
1303 return 0; in vop3_scale_factor()
1315 for (i = 0; i < 100; i++) { in vop3_scale_factor()
1319 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); in vop3_scale_factor()
1323 for (i = 0; i < 100; i++) { in vop3_scale_factor()
1327 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); in vop3_scale_factor()
1351 int i = 0; in vop2_get_primary_plane()
1353 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_get_primary_plane()
1358 return vop2->data->vp_primary_plane_order[0]; in vop2_get_primary_plane()
1404 u32 val = 0; in vop2_grf_writel()
1602 int i = 0; in vop2_find_win_by_phys_id()
1604 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_find_win_by_phys_id()
1614 int i = 0; in vop2_find_pd_data_by_id()
1616 for (i = 0; i < vop2->data->nr_pd; i++) { in vop2_find_pd_data_by_id()
1627 u32 vp_offset = crtc_id * 0x100; in rk3568_vop2_load_lut()
1634 for (i = 0; i < lut_len; i++) in rk3568_vop2_load_lut()
1644 u32 vp_offset = crtc_id * 0x100; in rk3588_vop2_load_lut()
1651 for (i = 0; i < lut_len; i++) in rk3588_vop2_load_lut()
1667 int i, lut_len, ret = 0; in rockchip_vop2_gamma_lut_init()
1676 return 0; in rockchip_vop2_gamma_lut_init()
1680 return 0; in rockchip_vop2_gamma_lut_init()
1683 return 0; in rockchip_vop2_gamma_lut_init()
1692 return 0; in rockchip_vop2_gamma_lut_init()
1697 return 0; in rockchip_vop2_gamma_lut_init()
1700 for (i = 0; i < lut_len; i++) { in rockchip_vop2_gamma_lut_init()
1701 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; in rockchip_vop2_gamma_lut_init()
1702 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; in rockchip_vop2_gamma_lut_init()
1703 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; in rockchip_vop2_gamma_lut_init()
1720 return 0; in rockchip_vop2_gamma_lut_init()
1729 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init()
1734 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) in rockchip_vop2_cubic_lut_init()
1735 return 0; in rockchip_vop2_cubic_lut_init()
1738 return 0; in rockchip_vop2_cubic_lut_init()
1743 for (i = 0; i < cubic_lut_len / 2; i++) { in rockchip_vop2_cubic_lut_init()
1744 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + in rockchip_vop2_cubic_lut_init()
1745 ((lut->lgreen[2 * i] & 0xfff) << 12) + in rockchip_vop2_cubic_lut_init()
1746 ((lut->lblue[2 * i] & 0xff) << 24); in rockchip_vop2_cubic_lut_init()
1747 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + in rockchip_vop2_cubic_lut_init()
1748 ((lut->lred[2 * i + 1] & 0xfff) << 4) + in rockchip_vop2_cubic_lut_init()
1749 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + in rockchip_vop2_cubic_lut_init()
1750 ((lut->lblue[2 * i + 1] & 0xf) << 28); in rockchip_vop2_cubic_lut_init()
1751 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; in rockchip_vop2_cubic_lut_init()
1752 *cubic_lut_addr++ = 0; in rockchip_vop2_cubic_lut_init()
1756 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + in rockchip_vop2_cubic_lut_init()
1757 ((lut->lgreen[2 * i] & 0xfff) << 12) + in rockchip_vop2_cubic_lut_init()
1758 ((lut->lblue[2 * i] & 0xff) << 24); in rockchip_vop2_cubic_lut_init()
1759 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; in rockchip_vop2_cubic_lut_init()
1760 *cubic_lut_addr++ = 0; in rockchip_vop2_cubic_lut_init()
1761 *cubic_lut_addr = 0; in rockchip_vop2_cubic_lut_init()
1773 return 0; in rockchip_vop2_cubic_lut_init()
1780 u32 vp_offset = crtc_id * 0x100; in vop2_bcsh_reg_update()
1794 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); in vop2_bcsh_reg_update()
1805 bcsh_state->saturation * bcsh_state->contrast / 0x100, false); in vop2_bcsh_reg_update()
1851 brightness = interpolate(0, -128, 100, 127, in vop2_tv_config_update()
1854 brightness = interpolate(0, -32, 100, 31, in vop2_tv_config_update()
1856 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); in vop2_tv_config_update()
1857 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); in vop2_tv_config_update()
1858 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); in vop2_tv_config_update()
1862 * a:[-30~0): in vop2_tv_config_update()
1863 * sin_hue = 0x100 - sin(a)*256; in vop2_tv_config_update()
1865 * a:[0~30] in vop2_tv_config_update()
1906 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop2_setup_dly_for_vp()
1924 ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, 0, false); in vop3_setup_pipe_dly()
1931 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
1933 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop3_setup_pipe_dly()
1941 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config()
1973 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) in vop2_post_config()
2001 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config()
2009 POST_ACM_BYPASS_EN_MASK, POST_ACM_BYPASS_EN_SHIFT, 0, false); in vop3_post_acm_config()
2011 writel(0, vop2->regs + RK3528_ACM_CTRL); in vop3_post_acm_config()
2019 value = (acm->acm_enable & 0x1) + ((mode->hdisplay & 0xfff) << 8) + in vop3_post_acm_config()
2020 ((mode->vdisplay & 0xfff) << 20); in vop3_post_acm_config()
2023 value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) + in vop3_post_acm_config()
2024 ((acm->s_gain << 20) & 0x3ff00000); in vop3_post_acm_config()
2027 lut_y = &acm->gain_lut_hy[0]; in vop3_post_acm_config()
2030 for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) { in vop3_post_acm_config()
2031 value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) + in vop3_post_acm_config()
2032 ((lut_s[i] << 16) & 0xff0000); in vop3_post_acm_config()
2036 lut_y = &acm->gain_lut_hs[0]; in vop3_post_acm_config()
2039 for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) { in vop3_post_acm_config()
2040 value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) + in vop3_post_acm_config()
2041 ((lut_s[i] << 16) & 0xff0000); in vop3_post_acm_config()
2045 lut_y = &acm->delta_lut_h[0]; in vop3_post_acm_config()
2048 for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) { in vop3_post_acm_config()
2049 value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) + in vop3_post_acm_config()
2050 ((lut_s[i] << 20) & 0x3ff00000); in vop3_post_acm_config()
2068 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config()
2108 value = csc_coef.csc_coef01 & 0xffff; in vop3_post_csc_config()
2109 value |= (csc_coef.csc_coef02 << 16) & 0xffff0000; in vop3_post_csc_config()
2111 value = csc_coef.csc_coef10 & 0xffff; in vop3_post_csc_config()
2112 value |= (csc_coef.csc_coef11 << 16) & 0xffff0000; in vop3_post_csc_config()
2114 value = csc_coef.csc_coef12 & 0xffff; in vop3_post_csc_config()
2115 value |= (csc_coef.csc_coef20 << 16) & 0xffff0000; in vop3_post_csc_config()
2117 value = csc_coef.csc_coef21 & 0xffff; in vop3_post_csc_config()
2118 value |= (csc_coef.csc_coef22 << 16) & 0xffff0000; in vop3_post_csc_config()
2124 range_type = csc_coef.range_type ? 0 : 1; in vop3_post_csc_config()
2125 range_type <<= is_input_yuv ? 0 : 1; in vop3_post_csc_config()
2131 POST_R2Y_EN_MASK, POST_R2Y_EN_SHIFT, post_r2y_en ? 1 : 0, false); in vop3_post_csc_config()
2133 POST_CSC_EN_MASK, POST_CSC_EN_SHIFT, post_csc_en ? 1 : 0, false); in vop3_post_csc_config()
2162 * Return value: 1 for power on, 0 for power off;
2166 int val = 0; in vop2_wait_power_domain_on()
2167 int shift = 0; in vop2_wait_power_domain_on()
2168 int shift_factor = 0; in vop2_wait_power_domain_on()
2186 ((val >> shift) & 0x1), 50 * 1000); in vop2_wait_power_domain_on()
2191 !((val >> shift) & 0x1), 50 * 1000); in vop2_wait_power_domain_on()
2198 int ret = 0; in vop2_power_domain_on()
2201 return 0; in vop2_power_domain_on()
2218 RK3588_CLUSTER0_PD_EN_SHIFT + generic_ffs(pd_id) - 1, 0, false); in vop2_power_domain_on()
2225 return 0; in vop2_power_domain_on()
2231 int i = 0; in rk3588_vop2_regsbak()
2236 for (i = 0; i < (vop2->reg_len >> 2); i++) in rk3588_vop2_regsbak()
2243 int layer_phy_id = 0; in vop3_overlay_init()
2245 u32 ovl_port_offset = 0; in vop3_overlay_init()
2246 u32 layer_nr = 0; in vop3_overlay_init()
2247 u8 shift = 0; in vop3_overlay_init()
2250 for (i = 0; i < vop2->data->nr_vps; i++) { in vop3_overlay_init()
2251 shift = 0; in vop3_overlay_init()
2252 ovl_port_offset = 0x100 * i; in vop3_overlay_init()
2254 for (j = 0; j < layer_nr; j++) { in vop3_overlay_init()
2264 for (i = 0; i < vop2->data->nr_vps; i++) { in vop3_overlay_init()
2266 for (j = 0; j < layer_nr; j++) { in vop3_overlay_init()
2282 int layer_phy_id = 0; in vop2_overlay_init()
2283 int total_used_layer = 0; in vop2_overlay_init()
2284 int port_mux = 0; in vop2_overlay_init()
2286 u32 layer_nr = 0; in vop2_overlay_init()
2287 u8 shift = 0; in vop2_overlay_init()
2290 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2292 for (j = 0; j < layer_nr; j++) { in vop2_overlay_init()
2302 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2304 for (j = 0; j < layer_nr; j++) { in vop2_overlay_init()
2318 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_overlay_init()
2358 u8 scale_engine_num = 0; in vop3_init_esmart_scale_engine()
2361 for (i = 0; i < vop2->data->nr_layers; i++) { in vop3_init_esmart_scale_engine()
2374 int layer_phy_id = 0; in vop2_global_initial()
2377 u32 layer_nr = 0; in vop2_global_initial()
2391 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2403 for (j = 0; j < layer_nr; j++) { in vop2_global_initial()
2411 int active_vp_num = 0; in vop2_global_initial()
2413 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2424 * For rk3528, one display policy for hdmi store in plane_mask[0], and the other in vop2_global_initial()
2436 j = 0; in vop2_global_initial()
2438 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2440 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ in vop2_global_initial()
2447 if (main_vp_index < 0) { in vop2_global_initial()
2448 main_vp_index = 0; in vop2_global_initial()
2449 vop2->vp_plane_mask[0] = plane_mask[0]; in vop2_global_initial()
2452 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ in vop2_global_initial()
2456 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2463 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2465 for (j = 0; j < layer_nr; j++) { in vop2_global_initial()
2482 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
2484 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) in vop2_global_initial()
2498 * VOP3_ESMART_8K_MODE = 0, in vop2_global_initial()
2508 if (ret < 0) in vop2_global_initial()
2516 DSP_VS_T_SEL_SHIFT, 0, false); in vop2_global_initial()
2520 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); in vop2_global_initial()
2530 return 0; in vop2_initial()
2546 memset(rockchip_vop2, 0, sizeof(struct vop2)); in rockchip_vop2_preinit()
2554 if (rockchip_vop2->grf <= 0) in rockchip_vop2_preinit()
2563 if (rockchip_vop2->vop_grf <= 0) in rockchip_vop2_preinit()
2566 rockchip_vop2->vo1_grf = regmap_get_range(map, 0); in rockchip_vop2_preinit()
2567 if (rockchip_vop2->vo1_grf <= 0) in rockchip_vop2_preinit()
2570 if (rockchip_vop2->sys_pmu <= 0) in rockchip_vop2_preinit()
2581 return 0; in rockchip_vop2_preinit()
2598 return 0; in vop2_calc_dclk()
2755 return 0; in vop2_calc_dsc_clk()
2765 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg()
2768 int if_pixclk_div = 0; in rk3588_vop2_if_cfg()
2769 int if_dclk_div = 0; in rk3588_vop2_if_cfg()
2774 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; in rk3588_vop2_if_cfg()
2775 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; in rk3588_vop2_if_cfg()
2777 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); in rk3588_vop2_if_cfg()
2778 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); in rk3588_vop2_if_cfg()
2786 return 0; in rk3588_vop2_if_cfg()
2792 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; in rk3588_vop2_if_cfg()
2805 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2810 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2815 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
2821 val = 0; in rk3588_vop2_if_cfg()
2845 val = 0; in rk3588_vop2_if_cfg()
2982 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
2984 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
2996 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_if_cfg()
3000 dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; in rk3568_vop2_if_cfg()
3001 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); in rk3568_vop2_if_cfg()
3002 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); in rk3568_vop2_if_cfg()
3134 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); in rk3528_vop2_if_cfg()
3135 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); in rk3528_vop2_if_cfg()
3168 dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; in rk3562_vop2_if_cfg()
3169 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); in rk3562_vop2_if_cfg()
3170 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); in rk3562_vop2_if_cfg()
3213 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap()
3215 u32 data_swap = 0; in vop2_post_color_swap()
3234 int ret = 0; in vop2_clk_set_parent()
3238 if (ret < 0) in vop2_clk_set_parent()
3245 int ret = 0; in vop2_clk_set_rate()
3249 if (ret < 0) in vop2_clk_set_rate()
3278 u32 decoder_regs_offset = (dsc_id * 0x100); in vop2_load_pps()
3279 int i = 0; in vop2_load_pps()
3283 if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { in vop2_load_pps()
3284 config_pps.pps_3 &= 0xf0; in vop2_load_pps()
3287 dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf); in vop2_load_pps()
3290 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in vop2_load_pps()
3292 (pps->rc_range_parameters[i] >> 3 & 0x1f) | in vop2_load_pps()
3293 ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | in vop2_load_pps()
3294 ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | in vop2_load_pps()
3295 ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); in vop2_load_pps()
3298 for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) in vop2_load_pps()
3311 u8 dsc_interface_mode = 0; in vop2_dsc_enable()
3321 u32 ctrl_regs_offset = (dsc_id * 0x30); in vop2_dsc_enable()
3322 u32 decoder_regs_offset = (dsc_id * 0x100); in vop2_dsc_enable()
3323 int dsc_txp_clk_div = 0; in vop2_dsc_enable()
3324 int dsc_pxl_clk_div = 0; in vop2_dsc_enable()
3325 int dsc_cds_clk_div = 0; in vop2_dsc_enable()
3326 int val = 0; in vop2_dsc_enable()
3358 DSC_MAN_MODE_SHIFT, 0, false); in vop2_dsc_enable()
3385 u32 dly_num, dsc_cds_rate_mhz, val = 0; in vop2_dsc_enable()
3418 int dsc_buf_size = dsc_id == 0 ? 4320 * 8 : 9216 * 2; in vop2_dsc_enable()
3430 DSC_INIT_DLY_MODE_SHIFT, 0, false); in vop2_dsc_enable()
3467 ((dsc_sink_cap->version_minor == 2 ? 1 : 0) << DSC_IFEP_SHIFT); in vop2_dsc_enable()
3500 ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0, in is_extend_pll()
3501 0, &args); in is_extend_pll()
3526 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup()
3548 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup()
3572 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd()
3583 AUTO_GATING_EN_SHIFT, 0, false); in rockchip_vop2_send_mcu_cmd()
3585 PORT_DCLK_AUTO_GATING_EN_SHIFT, 0, false); in rockchip_vop2_send_mcu_cmd()
3588 STANDBY_EN_SHIFT, 0, false); in rockchip_vop2_send_mcu_cmd()
3596 MCU_RS_SHIFT, 0, false); in rockchip_vop2_send_mcu_cmd()
3612 MCU_BYPASS_SHIFT, value ? 1 : 0, false); in rockchip_vop2_send_mcu_cmd()
3634 return 0; in rockchip_vop2_send_mcu_cmd()
3667 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init()
3670 u8 dither_down_en = 0; in rockchip_vop2_init()
3671 u8 dither_down_mode = 0; in rockchip_vop2_init()
3672 u8 pre_dither_down_en = 0; in rockchip_vop2_init()
3673 u8 dclk_div_factor = 0; in rockchip_vop2_init()
3674 char output_type_name[30] = {0}; in rockchip_vop2_init()
3682 unsigned long dclk_rate = 0; in rockchip_vop2_init()
3745 dither_down_en = 0; in rockchip_vop2_init()
3750 dither_down_en = 0; in rockchip_vop2_init()
3751 pre_dither_down_en = 0; in rockchip_vop2_init()
3759 dither_down_en = 0; in rockchip_vop2_init()
3773 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; in rockchip_vop2_init()
3807 INTERLACE_EN_SHIFT, 0, false); in rockchip_vop2_init()
3809 P2I_EN_SHIFT, 0, false); in rockchip_vop2_init()
3821 CORE_DCLK_DIV_EN_SHIFT, 0, false); in rockchip_vop2_init()
3825 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); in rockchip_vop2_init()
3828 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); in rockchip_vop2_init()
3834 val = 0x20010200; in rockchip_vop2_init()
3836 val = 0; in rockchip_vop2_init()
3842 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); in rockchip_vop2_init()
3859 vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL); in rockchip_vop2_init()
3893 "#clock-cells", 0, 0, &args); in rockchip_vop2_init()
3932 writel((BIT(0) << 16) | BIT(0), cru_base + 0x450); in rockchip_vop2_init()
3968 return 0; in rockchip_vop2_init()
3977 uint8_t xgt2 = 0, xgt4 = 0; in vop2_setup_scale()
3978 uint8_t ygt2 = 0, ygt4 = 0; in vop2_setup_scale()
3979 uint32_t xfac = 0, yfac = 0; in vop2_setup_scale()
4019 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) { in vop2_setup_scale()
4047 XGT_MODE_MASK, CLUSTER_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false); in vop2_setup_scale()
4070 AVG2_MASK, CLUSTER_AVG2_SHIFT, 0, false); in vop2_setup_scale()
4072 AVG4_MASK, CLUSTER_AVG4_SHIFT, 0, false); in vop2_setup_scale()
4075 YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, 0, false); in vop2_setup_scale()
4077 YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, 0, false); in vop2_setup_scale()
4093 XGT_MODE_MASK, ESMART_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false); in vop2_setup_scale()
4159 int y_mirror = 0; in vop2_set_cluster_win()
4163 u32 splice_pixel_offset = 0; in vop2_set_cluster_win()
4164 u32 splice_yrgb_offset = 0; in vop2_set_cluster_win()
4182 act_info |= (src_w - 1) & 0xffff; in vop2_set_cluster_win()
4185 dsp_info |= (crtc_w - 1) & 0xffff; in vop2_set_cluster_win()
4189 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); in vop2_set_cluster_win()
4194 y_mirror = 0; in vop2_set_cluster_win()
4252 int y_mirror = 0; in vop2_set_smart_win()
4256 u32 splice_pixel_offset = 0; in vop2_set_smart_win()
4257 u32 splice_yrgb_offset = 0; in vop2_set_smart_win()
4278 if (src_w > crtc_w && (src_w & 0xf) == 1) { in vop2_set_smart_win()
4284 act_info |= (src_w - 1) & 0xffff; in vop2_set_smart_win()
4287 dsp_info |= (crtc_w - 1) & 0xffff; in vop2_set_smart_win()
4291 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); in vop2_set_smart_win()
4296 y_mirror = 0; in vop2_set_smart_win()
4355 if (left_dst_w < 0) in vop2_calc_display_rect_for_splice()
4356 left_dst_w = 0; in vop2_calc_display_rect_for_splice()
4395 char plane_name[10] = {0}; in rockchip_vop2_set_plane()
4443 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", in rockchip_vop2_set_plane()
4449 return 0; in rockchip_vop2_set_plane()
4454 return 0; in rockchip_vop2_prepare()
4463 u32 ctrl_regs_offset = (dsc_id * 0x30); in vop2_dsc_cfg_done()
4468 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, in vop2_dsc_cfg_done()
4480 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable()
4484 STANDBY_EN_SHIFT, 0, false); in rockchip_vop2_enable()
4496 MCU_HOLD_MODE_SHIFT, 0, false); in rockchip_vop2_enable()
4498 return 0; in rockchip_vop2_enable()
4505 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable()
4516 return 0; in rockchip_vop2_disable()
4523 int i = 0; in rockchip_vop2_get_cursor_plane()
4527 if (cursor_plane < 0) in rockchip_vop2_get_cursor_plane()
4534 for (i = 0; i < vop2->data->nr_layers; i++) { in rockchip_vop2_get_cursor_plane()
4542 for (i = 0; i < vop2->data->nr_layers; i++) { in rockchip_vop2_get_cursor_plane()
4551 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { in rockchip_vop2_get_cursor_plane()
4570 u32 plane_mask = 0; in rockchip_vop2_fixup_dts()
4571 int vp_id = 0; in rockchip_vop2_fixup_dts()
4575 return 0; in rockchip_vop2_fixup_dts()
4585 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", in rockchip_vop2_fixup_dts()
4594 if (cursor_plane_id >= 0) in rockchip_vop2_fixup_dts()
4602 return 0; in rockchip_vop2_fixup_dts()
4620 return 0; in rockchip_vop2_check()
4634 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { in rockchip_vop2_mode_valid()
4639 return 0; in rockchip_vop2_mode_valid()
4686 return 0; in rockchip_vop2_mode_fixup()
4713 if (hscale < 0 || vscale < 0) { in rockchip_vop2_plane_check()
4718 return 0; in rockchip_vop2_plane_check()
4726 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te()
4727 int val = 0; in rockchip_vop2_apply_soft_te()
4728 int ret = 0; in rockchip_vop2_apply_soft_te()
4731 (val >> EDPI_WMS_FS) & 0x1, 50 * 1000); in rockchip_vop2_apply_soft_te()
4757 return 0; in rockchip_vop2_apply_soft_te()
4773 for (i = 0; i < n; i++) { in rockchip_vop2_regs_dump()
4776 for (j = 0; j < 68;) { in rockchip_vop2_regs_dump()
4786 return 0; in rockchip_vop2_regs_dump()
4803 for (i = 0; i < n; i++) { in rockchip_vop2_active_regs_dump()
4813 for (j = 0; j < 68;) { in rockchip_vop2_active_regs_dump()
4823 return 0; in rockchip_vop2_active_regs_dump()
4827 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
4828 { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
4829 { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
4830 { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
4831 { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
4832 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
4833 { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
4834 { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
4835 { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
4836 { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
4837 { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
4838 { RK3528_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
4839 { RK3528_ACM_CTRL, "ACM", RK3528_ACM_CTRL, 0x1, 0, 1},
4914 .layer_sel_win_id = { 1, 0xff, 0xff, 0xff },
4915 .reg_offset = 0,
4916 .axi_id = 0,
4917 .axi_yrgb_id = 0x06,
4918 .axi_uv_id = 0x07,
4934 .layer_sel_win_id = { 2, 0xff, 0xff, 0xff },
4935 .reg_offset = 0x200,
4936 .axi_id = 0,
4937 .axi_yrgb_id = 0x08,
4938 .axi_uv_id = 0x09,
4954 .layer_sel_win_id = { 3, 0, 0xff, 0xff },
4955 .reg_offset = 0x400,
4956 .axi_id = 0,
4957 .axi_yrgb_id = 0x0a,
4958 .axi_uv_id = 0x0b,
4974 .layer_sel_win_id = { 0xff, 1, 0xff, 0xff },
4975 .reg_offset = 0x600,
4976 .axi_id = 0,
4977 .axi_yrgb_id = 0x0c,
4978 .axi_uv_id = 0x0d,
4993 .win_sel_port_offset = 0,
4994 .layer_sel_win_id = { 0, 0xff, 0xff, 0xff },
4995 .reg_offset = 0,
4996 .axi_id = 0,
4997 .axi_yrgb_id = 0x02,
4998 .axi_uv_id = 0x03,
5023 .hdr_mix_dly = 0,
5033 .plane_mask = rk3528_vp_plane_mask[0],
5045 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5046 { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
5047 { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5048 { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5049 { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5050 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5051 { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5052 { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5053 { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
5054 { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
5115 .layer_sel_win_id = { 0, 0, 0xff, 0xff },
5116 .reg_offset = 0,
5117 .axi_id = 0,
5118 .axi_yrgb_id = 0x02,
5119 .axi_uv_id = 0x03,
5133 .layer_sel_win_id = { 1, 1, 0xff, 0xff },
5134 .reg_offset = 0x200,
5135 .axi_id = 0,
5136 .axi_yrgb_id = 0x04,
5137 .axi_uv_id = 0x05,
5151 .layer_sel_win_id = { 2, 2, 0xff, 0xff },
5152 .reg_offset = 0x400,
5153 .axi_id = 0,
5154 .axi_yrgb_id = 0x06,
5155 .axi_uv_id = 0x07,
5169 .layer_sel_win_id = { 3, 3, 0xff, 0xff },
5170 .reg_offset = 0x600,
5171 .axi_id = 0,
5172 .axi_yrgb_id = 0x08,
5173 .axi_uv_id = 0x0d,
5203 .plane_mask = rk3562_vp_plane_mask[0],
5215 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5216 { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
5217 { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5218 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5219 { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
5220 { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
5221 { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
5222 { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5223 { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5224 { RK3568_SMART0_CTRL0, "Smart0", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
5225 { RK3568_SMART1_CTRL0, "Smart1", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
5226 { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
5314 .win_sel_port_offset = 0,
5315 .layer_sel_win_id = { 0, 0, 0, 0xff },
5316 .reg_offset = 0,
5330 .layer_sel_win_id = { 1, 1, 1, 0xff },
5331 .reg_offset = 0x200,
5345 .layer_sel_win_id = { 2, 2, 2, 0xff },
5346 .reg_offset = 0,
5360 .layer_sel_win_id = { 6, 6, 6, 0xff },
5361 .reg_offset = 0x200,
5375 .layer_sel_win_id = { 3, 3, 3, 0xff },
5376 .reg_offset = 0x400,
5390 .layer_sel_win_id = { 7, 7, 7, 0xff },
5391 .reg_offset = 0x600,
5408 .feature = 0,
5413 .feature = 0,
5424 .plane_mask = rk356x_vp_plane_mask[0],
5457 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5458 { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
5459 { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5460 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5461 { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
5462 { RK3588_VP3_DSP_CTRL, "VP3", RK3588_VP3_DSP_CTRL, 0x1, 31, 0 },
5463 { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
5464 { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
5465 { RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0, 1 },
5466 { RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0, 1 },
5467 { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5468 { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5469 { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
5470 { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
5471 { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
5572 .win_sel_port_offset = 0,
5573 .layer_sel_win_id = { 0, 0, 0, 0 },
5574 .reg_offset = 0,
5575 .axi_id = 0,
5593 .reg_offset = 0x200,
5594 .axi_id = 0,
5613 .reg_offset = 0x400,
5632 .reg_offset = 0x600,
5652 .reg_offset = 0,
5653 .axi_id = 0,
5654 .axi_yrgb_id = 0x0a,
5655 .axi_uv_id = 0x0b,
5670 .reg_offset = 0x200,
5671 .axi_id = 0,
5672 .axi_yrgb_id = 0x0c,
5673 .axi_uv_id = 0x0d,
5690 .reg_offset = 0x400,
5692 .axi_yrgb_id = 0x0a,
5693 .axi_uv_id = 0x0b,
5709 .reg_offset = 0x600,
5711 .axi_yrgb_id = 0x0c,
5712 .axi_uv_id = 0x0d,
5724 {0x00000000, "no error detected by DSC encoder"},
5725 {0x0030ffff, "bits per component error"},
5726 {0x0040ffff, "multiple mode error"},
5727 {0x0050ffff, "line buffer depth error"},
5728 {0x0060ffff, "minor version error"},
5729 {0x0070ffff, "picture height error"},
5730 {0x0080ffff, "picture width error"},
5731 {0x0090ffff, "number of slices error"},
5732 {0x00c0ffff, "slice height Error "},
5733 {0x00d0ffff, "slice width error"},
5734 {0x00e0ffff, "second line BPG offset error"},
5735 {0x00f0ffff, "non second line BPG offset error"},
5736 {0x0100ffff, "PPS ID error"},
5737 {0x0110ffff, "bits per pixel (BPP) Error"},
5738 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */
5740 {0x01510001, "slice 0 RC buffer model overflow error"},
5741 {0x01510002, "slice 1 RC buffer model overflow error"},
5742 {0x01510004, "slice 2 RC buffer model overflow error"},
5743 {0x01510008, "slice 3 RC buffer model overflow error"},
5744 {0x01510010, "slice 4 RC buffer model overflow error"},
5745 {0x01510020, "slice 5 RC buffer model overflow error"},
5746 {0x01510040, "slice 6 RC buffer model overflow error"},
5747 {0x01510080, "slice 7 RC buffer model overflow error"},
5749 {0x01610001, "slice 0 RC buffer model underflow error"},
5750 {0x01610002, "slice 1 RC buffer model underflow error"},
5751 {0x01610004, "slice 2 RC buffer model underflow error"},
5752 {0x01610008, "slice 3 RC buffer model underflow error"},
5753 {0x01610010, "slice 4 RC buffer model underflow error"},
5754 {0x01610020, "slice 5 RC buffer model underflow error"},
5755 {0x01610040, "slice 6 RC buffer model underflow error"},
5756 {0x01610080, "slice 7 RC buffer model underflow error"},
5758 {0xffffffff, "unsuccessful RESET cycle status"},
5759 {0x00a0ffff, "ICH full error precision settings error"},
5760 {0x0020ffff, "native mode"},
5764 {0x00000000, "rate buffer status"},
5765 {0x00000001, "line buffer status"},
5766 {0x00000002, "decoder model status"},
5767 {0x00000003, "pixel buffer status"},
5768 {0x00000004, "balance fifo buffer status"},
5769 {0x00000005, "syntax element fifo status"},
5819 .feature = 0,
5867 .plane_mask = rk3588_vp_plane_mask[0],