172 	struct phy_config *phy_cfg;  member
203 			const struct phy_config *phy_cfg);
448 	const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;  in inno_hdmi_phy_power_on()  local
454 	if (inno->phy_cfg)  in inno_hdmi_phy_power_on()
455 		phy_cfg = inno->phy_cfg;  in inno_hdmi_phy_power_on()
478 	for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++)  in inno_hdmi_phy_power_on()
479 		if (tmdsclock <= phy_cfg->tmdsclock)  in inno_hdmi_phy_power_on()
482 	if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL)  in inno_hdmi_phy_power_on()
487 		return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);  in inno_hdmi_phy_power_on()
574 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3228_power_on()  argument
613 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
722 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3328_power_on()  argument
746 		inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);  in inno_hdmi_phy_rk3328_power_on()
760 	if (phy_cfg->tmdsclock > 340000000) {  in inno_hdmi_phy_rk3328_power_on()
767 	} else if (phy_cfg->tmdsclock > 165000000) {  in inno_hdmi_phy_rk3328_power_on()
781 	val = 47520000000UL / phy_cfg->tmdsclock;  in inno_hdmi_phy_rk3328_power_on()
801 	if (phy_cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3328_power_on()
915 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3528_power_on()  argument
942 	val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1];  in inno_hdmi_phy_rk3528_power_on()
946 	val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1];  in inno_hdmi_phy_rk3528_power_on()
950 	inno_write(inno, 0xb5, phy_cfg->regs[2]);  in inno_hdmi_phy_rk3528_power_on()
951 	inno_write(inno, 0xb6, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
952 	inno_write(inno, 0xb7, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
953 	inno_write(inno, 0xb8, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
956 	inno_write(inno, 0xbb, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
957 	inno_write(inno, 0xbc, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
958 	inno_write(inno, 0xbd, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
979 	if (phy_cfg->tmdsclock > 340000000) {  in inno_hdmi_phy_rk3528_power_on()
1001 	if (phy_cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3528_power_on()
1139 			       struct phy_config *phy_cfg,  in inno_hdmi_update_phy_table()  argument
1145 		phy_cfg[i].tmdsclock =  in inno_hdmi_update_phy_table()
1148 		debug("%ld ", phy_cfg[i].tmdsclock);  in inno_hdmi_update_phy_table()
1150 			phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j];  in inno_hdmi_update_phy_table()
1151 			debug("0x%02x ", phy_cfg[i].regs[j]);  in inno_hdmi_update_phy_table()
1160 	phy_cfg[i].tmdsclock = ~0UL;  in inno_hdmi_update_phy_table()
1162 		phy_cfg[i].regs[j] = 0;  in inno_hdmi_update_phy_table()
1275 		inno->phy_cfg = malloc(val + PHY_TAB_LEN);  in inno_hdmi_phy_init()
1276 		if (!inno->phy_cfg) {  in inno_hdmi_phy_init()
1284 						 inno->phy_cfg,  in inno_hdmi_phy_init()
1370 	if (!inno->phy_cfg)  in inno_hdmi_phy_clk_round_rate()
1374 	for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {  in inno_hdmi_phy_clk_round_rate()
1375 		if (inno->phy_cfg[i].tmdsclock >= tmdsclock)  in inno_hdmi_phy_clk_round_rate()
1379 	if (inno->phy_cfg[i].tmdsclock == ~0UL)  in inno_hdmi_phy_clk_round_rate()