345 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)  in inno_write()  function
367 	inno_write(inno, reg, tmp);  in inno_update_bits()
594 	inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
613 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
672 	inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_pre_pll_update()
715 	inno_write(inno, 0x01, 0x07);  in inno_hdmi_phy_rk3328_init()
716 	inno_write(inno, 0x02, 0x91);  in inno_hdmi_phy_rk3328_init()
732 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3328_power_on()
734 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3328_power_on()
736 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
739 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3328_power_on()
741 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
742 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3328_power_on()
746 		inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);  in inno_hdmi_phy_rk3328_power_on()
755 	inno_write(inno, 0xc8, 0);  in inno_hdmi_phy_rk3328_power_on()
756 	inno_write(inno, 0xc9, 0);  in inno_hdmi_phy_rk3328_power_on()
757 	inno_write(inno, 0xca, 0);  in inno_hdmi_phy_rk3328_power_on()
758 	inno_write(inno, 0xcb, 0);  in inno_hdmi_phy_rk3328_power_on()
763 		inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80);  in inno_hdmi_phy_rk3328_power_on()
764 		inno_write(inno, 0xc6, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
765 		inno_write(inno, 0xc7, 3 << 1);  in inno_hdmi_phy_rk3328_power_on()
766 		inno_write(inno, 0xc5, ((val >> 8) & 0xff));  in inno_hdmi_phy_rk3328_power_on()
768 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
772 		inno_write(inno, 0xc8, 0x30);  in inno_hdmi_phy_rk3328_power_on()
773 		inno_write(inno, 0xc9, 0x10);  in inno_hdmi_phy_rk3328_power_on()
774 		inno_write(inno, 0xca, 0x10);  in inno_hdmi_phy_rk3328_power_on()
775 		inno_write(inno, 0xcb, 0x10);  in inno_hdmi_phy_rk3328_power_on()
777 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
782 	inno_write(inno, 0xd8, (val >> 8) & 0xff);  in inno_hdmi_phy_rk3328_power_on()
783 	inno_write(inno, 0xd9, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
789 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3328_power_on()
812 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3328_power_off()
829 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3328_pre_pll_update()
834 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
835 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3328_pre_pll_update()
838 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
841 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
845 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
849 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
851 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
853 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
855 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
856 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
857 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
925 	inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3528_power_on()
928 		inno_write(inno, 0xad, 0x8);  in inno_hdmi_phy_rk3528_power_on()
929 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3528_power_on()
932 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3528_power_on()
933 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3528_power_on()
937 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3528_power_on()
943 	inno_write(inno, 0xbf, val);  in inno_hdmi_phy_rk3528_power_on()
947 	inno_write(inno, 0xc0, val);  in inno_hdmi_phy_rk3528_power_on()
950 	inno_write(inno, 0xb5, phy_cfg->regs[2]);  in inno_hdmi_phy_rk3528_power_on()
951 	inno_write(inno, 0xb6, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
952 	inno_write(inno, 0xb7, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
953 	inno_write(inno, 0xb8, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
956 	inno_write(inno, 0xbb, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
957 	inno_write(inno, 0xbc, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
958 	inno_write(inno, 0xbd, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
961 	inno_write(inno, 0xb4, 0x7);  in inno_hdmi_phy_rk3528_power_on()
964 	inno_write(inno, 0xbe, 0x70);  in inno_hdmi_phy_rk3528_power_on()
966 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
980 		inno_write(inno, 0xc7, 0x76);  in inno_hdmi_phy_rk3528_power_on()
981 		inno_write(inno, 0xc5, 0x83);  in inno_hdmi_phy_rk3528_power_on()
982 		inno_write(inno, 0xc8, 0x00);  in inno_hdmi_phy_rk3528_power_on()
983 		inno_write(inno, 0xc9, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
984 		inno_write(inno, 0xca, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
985 		inno_write(inno, 0xcb, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
987 		inno_write(inno, 0xc7, 0x76);  in inno_hdmi_phy_rk3528_power_on()
988 		inno_write(inno, 0xc5, 0x83);  in inno_hdmi_phy_rk3528_power_on()
989 		inno_write(inno, 0xc8, 0x00);  in inno_hdmi_phy_rk3528_power_on()
990 		inno_write(inno, 0xc9, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
991 		inno_write(inno, 0xca, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
992 		inno_write(inno, 0xcb, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
998 	inno_write(inno, 0xd8, (temp >> 8) & 0xff);  in inno_hdmi_phy_rk3528_power_on()
999 	inno_write(inno, 0xd9, temp & 0xff);  in inno_hdmi_phy_rk3528_power_on()
1008 	inno_write(inno, 0x05, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1009 	inno_write(inno, 0x07, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1010 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
1018 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3528_power_off()
1025 	inno_write(inno, 0x05, 0);  in inno_hdmi_phy_rk3528_power_off()
1026 	inno_write(inno, 0x07, 0);  in inno_hdmi_phy_rk3528_power_off()
1035 	inno_write(inno, 0x02, 0x81);  in inno_hdmi_phy_rk3528_init()
1045 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_pre_pll_update()
1051 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3528_pre_pll_update()
1056 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1057 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3528_pre_pll_update()
1060 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1063 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1067 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1071 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1073 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1075 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1077 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1078 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1079 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()