200 	void (*init)(struct inno_hdmi_phy *inno);
201 	int (*power_on)(struct inno_hdmi_phy *inno,
204 	void (*power_off)(struct inno_hdmi_phy *inno);
205 	int (*pre_pll_update)(struct inno_hdmi_phy *inno,
207 	unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno,
345 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)  in inno_write()  argument
347 	writel(val, inno->regs + (reg * 4));  in inno_write()
350 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)  in inno_read()  argument
354 	val = readl(inno->regs + (reg * 4));  in inno_read()
359 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,  in inno_update_bits()  argument
364 	orig = inno_read(inno, reg);  in inno_update_bits()
367 	inno_write(inno, reg, tmp);  in inno_update_bits()
370 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_get_tmdsclk()  argument
375 	switch (inno->bus_width) {  in inno_hdmi_phy_get_tmdsclk()
443 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_power_on()  local
445 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_power_on()
448 	const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;  in inno_hdmi_phy_power_on()
449 	u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);  in inno_hdmi_phy_power_on()
454 	if (inno->phy_cfg)  in inno_hdmi_phy_power_on()
455 		phy_cfg = inno->phy_cfg;  in inno_hdmi_phy_power_on()
462 	if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 &&  in inno_hdmi_phy_power_on()
465 	else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&  in inno_hdmi_phy_power_on()
468 	else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528)  in inno_hdmi_phy_power_on()
486 	if (inno->plat_data->ops->power_on)  in inno_hdmi_phy_power_on()
487 		return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);  in inno_hdmi_phy_power_on()
495 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_power_off()  local
497 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_power_off()
500 	if (inno->plat_data->ops->power_off)  in inno_hdmi_phy_power_off()
501 		inno->plat_data->ops->power_off(inno);  in inno_hdmi_phy_power_off()
507 static int inno_hdmi_phy_clk_is_prepared(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_clk_is_prepared()  argument
511 	if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)  in inno_hdmi_phy_clk_is_prepared()
512 		status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK;  in inno_hdmi_phy_clk_is_prepared()
514 		status = inno_read(inno, 0xa0) & 1;  in inno_hdmi_phy_clk_is_prepared()
519 static int inno_hdmi_phy_clk_prepare(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_clk_prepare()  argument
521 	if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)  in inno_hdmi_phy_clk_prepare()
522 		inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,  in inno_hdmi_phy_clk_prepare()
525 		inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_clk_prepare()
530 static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_clk_set_rate()  argument
534 	u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);  in inno_hdmi_phy_clk_set_rate()
545 	if (inno->plat_data->ops->pre_pll_update)  in inno_hdmi_phy_clk_set_rate()
546 		inno->plat_data->ops->pre_pll_update(inno, cfg);  in inno_hdmi_phy_clk_set_rate()
548 	inno->pixclock = rate;  in inno_hdmi_phy_clk_set_rate()
553 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3228_init()  argument
564 	inno_update_bits(inno, 0x01, m, v);  in inno_hdmi_phy_rk3228_init()
565 	inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);  in inno_hdmi_phy_rk3228_init()
568 	inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);  in inno_hdmi_phy_rk3228_init()
572 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3228_power_on()  argument
580 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);  in inno_hdmi_phy_rk3228_power_on()
583 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
584 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
589 	inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
593 	inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
594 	inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
600 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
605 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
609 		inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
613 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
616 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
617 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
620 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
623 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
627 	while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) {  in inno_hdmi_phy_rk3228_power_on()
641 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
645 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3228_power_off()  argument
648 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
651 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
654 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_off()
658 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3228_pre_pll_update()  argument
665 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_pre_pll_update()
670 	inno_update_bits(inno, 0xe2, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
672 	inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_pre_pll_update()
677 	inno_update_bits(inno, 0xe4, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
682 	inno_update_bits(inno, 0xe5, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
689 	inno_update_bits(inno, 0xe6, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
692 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_pre_pll_update()
696 	while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) {  in inno_hdmi_phy_rk3228_pre_pll_update()
709 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3328_init()  argument
715 	inno_write(inno, 0x01, 0x07);  in inno_hdmi_phy_rk3328_init()
716 	inno_write(inno, 0x02, 0x91);  in inno_hdmi_phy_rk3328_init()
720 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3328_power_on()  argument
727 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
729 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
732 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3328_power_on()
734 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3328_power_on()
736 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
739 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3328_power_on()
741 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
742 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3328_power_on()
746 		inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);  in inno_hdmi_phy_rk3328_power_on()
755 	inno_write(inno, 0xc8, 0);  in inno_hdmi_phy_rk3328_power_on()
756 	inno_write(inno, 0xc9, 0);  in inno_hdmi_phy_rk3328_power_on()
757 	inno_write(inno, 0xca, 0);  in inno_hdmi_phy_rk3328_power_on()
758 	inno_write(inno, 0xcb, 0);  in inno_hdmi_phy_rk3328_power_on()
763 		inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80);  in inno_hdmi_phy_rk3328_power_on()
764 		inno_write(inno, 0xc6, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
765 		inno_write(inno, 0xc7, 3 << 1);  in inno_hdmi_phy_rk3328_power_on()
766 		inno_write(inno, 0xc5, ((val >> 8) & 0xff));  in inno_hdmi_phy_rk3328_power_on()
768 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
772 		inno_write(inno, 0xc8, 0x30);  in inno_hdmi_phy_rk3328_power_on()
773 		inno_write(inno, 0xc9, 0x10);  in inno_hdmi_phy_rk3328_power_on()
774 		inno_write(inno, 0xca, 0x10);  in inno_hdmi_phy_rk3328_power_on()
775 		inno_write(inno, 0xcb, 0x10);  in inno_hdmi_phy_rk3328_power_on()
777 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
782 	inno_write(inno, 0xd8, (val >> 8) & 0xff);  in inno_hdmi_phy_rk3328_power_on()
783 	inno_write(inno, 0xd9, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
786 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
788 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3328_power_on()
789 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3328_power_on()
793 		if (inno_read(inno, 0xaf) & 1)  in inno_hdmi_phy_rk3328_power_on()
797 	if (!(inno_read(inno, 0xaf) & 1)) {  in inno_hdmi_phy_rk3328_power_on()
804 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
809 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3328_power_off()  argument
812 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3328_power_off()
814 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3328_power_off()
816 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_off()
820 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3328_pre_pll_update()  argument
826 	inno_update_bits(inno, 0xa0, 1, 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
828 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
829 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3328_pre_pll_update()
834 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
835 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3328_pre_pll_update()
838 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
841 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
845 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
849 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
851 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
853 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
855 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
856 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
857 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
861 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
865 		if (inno_read(inno, 0xa9) & 1)  in inno_hdmi_phy_rk3328_pre_pll_update()
878 inno_hdmi_3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,  in inno_hdmi_3328_phy_pll_recalc_rate()  argument
886 	nd = inno_read(inno, 0xa1) & 0x3f;  in inno_hdmi_3328_phy_pll_recalc_rate()
887 	nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);  in inno_hdmi_3328_phy_pll_recalc_rate()
889 	if ((inno_read(inno, 0xa2) & 0x30) == 0) {  in inno_hdmi_3328_phy_pll_recalc_rate()
890 		frac = inno_read(inno, 0xd3) |  in inno_hdmi_3328_phy_pll_recalc_rate()
891 		       (inno_read(inno, 0xd2) << 8) |  in inno_hdmi_3328_phy_pll_recalc_rate()
892 		       (inno_read(inno, 0xd1) << 16);  in inno_hdmi_3328_phy_pll_recalc_rate()
895 	if (inno_read(inno, 0xa0) & 2) {  in inno_hdmi_3328_phy_pll_recalc_rate()
898 		no_a = inno_read(inno, 0xa5) & 0x1f;  in inno_hdmi_3328_phy_pll_recalc_rate()
899 		no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;  in inno_hdmi_3328_phy_pll_recalc_rate()
900 		no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7));  in inno_hdmi_3328_phy_pll_recalc_rate()
901 		no_d = inno_read(inno, 0xa6) & 0x1f;  in inno_hdmi_3328_phy_pll_recalc_rate()
907 	inno->pixclock = rate;  in inno_hdmi_3328_phy_pll_recalc_rate()
913 inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3528_power_on()  argument
919 	u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);  in inno_hdmi_phy_rk3528_power_on()
922 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
925 	inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3528_power_on()
928 		inno_write(inno, 0xad, 0x8);  in inno_hdmi_phy_rk3528_power_on()
929 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3528_power_on()
932 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3528_power_on()
933 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3528_power_on()
937 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3528_power_on()
939 	inno_update_bits(inno, 0xad, BIT(4), val);  in inno_hdmi_phy_rk3528_power_on()
943 	inno_write(inno, 0xbf, val);  in inno_hdmi_phy_rk3528_power_on()
947 	inno_write(inno, 0xc0, val);  in inno_hdmi_phy_rk3528_power_on()
950 	inno_write(inno, 0xb5, phy_cfg->regs[2]);  in inno_hdmi_phy_rk3528_power_on()
951 	inno_write(inno, 0xb6, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
952 	inno_write(inno, 0xb7, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
953 	inno_write(inno, 0xb8, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
956 	inno_write(inno, 0xbb, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
957 	inno_write(inno, 0xbc, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
958 	inno_write(inno, 0xbd, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
961 	inno_write(inno, 0xb4, 0x7);  in inno_hdmi_phy_rk3528_power_on()
964 	inno_write(inno, 0xbe, 0x70);  in inno_hdmi_phy_rk3528_power_on()
966 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
969 		if (inno_read(inno, 0xaf) & 1)  in inno_hdmi_phy_rk3528_power_on()
973 	if (!(inno_read(inno, 0xaf) & 1)) {  in inno_hdmi_phy_rk3528_power_on()
974 		dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");  in inno_hdmi_phy_rk3528_power_on()
980 		inno_write(inno, 0xc7, 0x76);  in inno_hdmi_phy_rk3528_power_on()
981 		inno_write(inno, 0xc5, 0x83);  in inno_hdmi_phy_rk3528_power_on()
982 		inno_write(inno, 0xc8, 0x00);  in inno_hdmi_phy_rk3528_power_on()
983 		inno_write(inno, 0xc9, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
984 		inno_write(inno, 0xca, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
985 		inno_write(inno, 0xcb, 0x2f);  in inno_hdmi_phy_rk3528_power_on()
987 		inno_write(inno, 0xc7, 0x76);  in inno_hdmi_phy_rk3528_power_on()
988 		inno_write(inno, 0xc5, 0x83);  in inno_hdmi_phy_rk3528_power_on()
989 		inno_write(inno, 0xc8, 0x00);  in inno_hdmi_phy_rk3528_power_on()
990 		inno_write(inno, 0xc9, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
991 		inno_write(inno, 0xca, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
992 		inno_write(inno, 0xcb, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
998 	inno_write(inno, 0xd8, (temp >> 8) & 0xff);  in inno_hdmi_phy_rk3528_power_on()
999 	inno_write(inno, 0xd9, temp & 0xff);  in inno_hdmi_phy_rk3528_power_on()
1004 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
1005 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3528_power_on()
1008 	inno_write(inno, 0x05, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1009 	inno_write(inno, 0x07, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1010 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
1015 static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3528_power_off()  argument
1018 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3528_power_off()
1020 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3528_power_off()
1022 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3528_power_off()
1025 	inno_write(inno, 0x05, 0);  in inno_hdmi_phy_rk3528_power_off()
1026 	inno_write(inno, 0x07, 0);  in inno_hdmi_phy_rk3528_power_off()
1029 static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno)  in inno_hdmi_phy_rk3528_init()  argument
1035 	inno_write(inno, 0x02, 0x81);  in inno_hdmi_phy_rk3528_init()
1039 inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno,  in inno_hdmi_phy_rk3528_pre_pll_update()  argument
1044 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3528_pre_pll_update()
1045 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_pre_pll_update()
1048 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1050 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3528_pre_pll_update()
1051 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3528_pre_pll_update()
1056 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1057 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3528_pre_pll_update()
1060 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1063 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1067 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1071 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1073 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1075 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1077 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1078 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1079 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1084 		if (inno_read(inno, 0xa9) & 1)  in inno_hdmi_phy_rk3528_pre_pll_update()
1089 		dev_err(inno->dev, "Pre-PLL unlock\n");  in inno_hdmi_phy_rk3528_pre_pll_update()
1097 inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,  in inno_hdmi_rk3528_phy_pll_recalc_rate()  argument
1105 	nd = inno_read(inno, 0xa1) & 0x3f;  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1106 	nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1108 	if ((inno_read(inno, 0xa2) & 0x30) == 0) {  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1109 		frac = inno_read(inno, 0xd3) |  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1110 		       (inno_read(inno, 0xd2) << 8) |  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1111 		       (inno_read(inno, 0xd1) << 16);  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1114 	if (inno_read(inno, 0xa0) & 2) {  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1117 		no_a = inno_read(inno, 0xa5) & 0x1f;  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1118 		no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1119 		no_d = inno_read(inno, 0xa6) & 0x1f;  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1127 	inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1129 	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);  in inno_hdmi_rk3528_phy_pll_recalc_rate()
1138 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config,  in inno_hdmi_update_phy_table()  argument
1225 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_init()  local
1228 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_init()
1236 	inno->regs = (void *)RK3528_HDMIPHY_BASE;  in inno_hdmi_phy_init()
1238 	inno->regs = dev_read_addr_ptr(dev);  in inno_hdmi_phy_init()
1239 	inno->node = dev->node;  in inno_hdmi_phy_init()
1241 	if (!inno->regs) {  in inno_hdmi_phy_init()
1253 			inno->plat_data = inno_hdmi_phy_of_match[i].data;  in inno_hdmi_phy_init()
1275 		inno->phy_cfg = malloc(val + PHY_TAB_LEN);  in inno_hdmi_phy_init()
1276 		if (!inno->phy_cfg) {  in inno_hdmi_phy_init()
1283 		ret = inno_hdmi_update_phy_table(inno, phy_config,  in inno_hdmi_phy_init()
1284 						 inno->phy_cfg,  in inno_hdmi_phy_init()
1299 	if (!inno->plat_data || !inno->plat_data->ops)  in inno_hdmi_phy_init()
1302 	if (inno->plat_data->ops->init)  in inno_hdmi_phy_init()
1303 		inno->plat_data->ops->init(inno);  in inno_hdmi_phy_init()
1312 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_set_pll()  local
1314 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_set_pll()
1318 	if (!inno)  in inno_hdmi_phy_set_pll()
1319 		inno = g_inno;  in inno_hdmi_phy_set_pll()
1321 	inno_hdmi_phy_clk_prepare(inno);  in inno_hdmi_phy_set_pll()
1322 	inno_hdmi_phy_clk_is_prepared(inno);  in inno_hdmi_phy_set_pll()
1323 	inno_hdmi_phy_clk_set_rate(inno, rate);  in inno_hdmi_phy_set_pll()
1331 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_set_bus_width()  local
1333 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_set_bus_width()
1336 	inno->bus_width = bus_width;  in inno_hdmi_phy_set_bus_width()
1345 	struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;  in inno_hdmi_phy_clk_round_rate()  local
1347 	struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);  in inno_hdmi_phy_clk_round_rate()
1351 	u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);  in inno_hdmi_phy_clk_round_rate()
1361 	if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&  in inno_hdmi_phy_clk_round_rate()
1370 	if (!inno->phy_cfg)  in inno_hdmi_phy_clk_round_rate()
1374 	for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {  in inno_hdmi_phy_clk_round_rate()
1375 		if (inno->phy_cfg[i].tmdsclock >= tmdsclock)  in inno_hdmi_phy_clk_round_rate()
1379 	if (inno->phy_cfg[i].tmdsclock == ~0UL)  in inno_hdmi_phy_clk_round_rate()
1417 	struct inno_hdmi_phy *inno = malloc(sizeof(struct inno_hdmi_phy));  in inno_spl_hdmi_phy_probe()  local
1419 	memset(inno, 0, sizeof(*inno));  in inno_spl_hdmi_phy_probe()
1420 	g_inno = inno;  in inno_spl_hdmi_phy_probe()
1423 	state->conn_state.connector->phy->data = (void *)inno;  in inno_spl_hdmi_phy_probe()
1429 	struct inno_hdmi_phy *inno = dev_get_priv(dev);  in inno_hdmi_phy_probe()  local
1433 	inno->dev = dev;  in inno_hdmi_phy_probe()
1436 	g_inno = inno;  in inno_hdmi_phy_probe()