Lines Matching +full:m +full:- +full:phy
2 * SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <clk-uclass.h>
22 #include <linux/media-bus-format.h>
227 /* global variables are used to pass reource from phy drivers to clk driver */
322 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
347 writel(val, inno->regs + (reg * 4)); in inno_write()
354 val = readl(inno->regs + (reg * 4)); in inno_read()
375 switch (inno->bus_width) { in inno_hdmi_phy_get_tmdsclk()
414 printf("%s: no misc-device found\n", __func__); in rk_get_cpu_version()
415 return -EINVAL; in rk_get_cpu_version()
418 node = dev_read_subnode(dev, "cpu-version"); in rk_get_cpu_version()
420 return -EINVAL; in rk_get_cpu_version()
425 return -EINVAL; in rk_get_cpu_version()
440 static int inno_hdmi_phy_power_on(struct rockchip_phy *phy) in inno_hdmi_phy_power_on() argument
443 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_power_on()
445 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_power_on()
448 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
449 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_power_on()
452 printf("start Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
454 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
455 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
459 return -EINVAL; in inno_hdmi_phy_power_on()
462 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && in inno_hdmi_phy_power_on()
465 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_power_on()
468 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_power_on()
473 for (; cfg->tmdsclock != ~0UL; cfg++) in inno_hdmi_phy_power_on()
474 if (tmdsclock <= cfg->tmdsclock && in inno_hdmi_phy_power_on()
475 cfg->version & chipversion) in inno_hdmi_phy_power_on()
478 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) in inno_hdmi_phy_power_on()
479 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
482 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) in inno_hdmi_phy_power_on()
483 return -EINVAL; in inno_hdmi_phy_power_on()
485 printf("Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
486 if (inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
487 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
489 return -EINVAL; in inno_hdmi_phy_power_on()
492 static int inno_hdmi_phy_power_off(struct rockchip_phy *phy) in inno_hdmi_phy_power_off() argument
495 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_power_off()
497 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_power_off()
500 if (inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
501 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
502 printf("Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
511 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_is_prepared()
521 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_prepare()
536 for (; cfg->pixclock != ~0UL; cfg++) in inno_hdmi_phy_clk_set_rate()
537 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) in inno_hdmi_phy_clk_set_rate()
540 if (cfg->pixclock == ~0UL) { in inno_hdmi_phy_clk_set_rate()
542 return -EINVAL; in inno_hdmi_phy_clk_set_rate()
545 if (inno->plat_data->ops->pre_pll_update) in inno_hdmi_phy_clk_set_rate()
546 inno->plat_data->ops->pre_pll_update(inno, cfg); in inno_hdmi_phy_clk_set_rate()
548 inno->pixclock = rate; in inno_hdmi_phy_clk_set_rate()
555 u32 m, v; in inno_hdmi_phy_rk3228_init() local
558 * Use phy internal register control in inno_hdmi_phy_rk3228_init()
561 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | in inno_hdmi_phy_rk3228_init()
564 inno_update_bits(inno, 0x01, m, v); in inno_hdmi_phy_rk3228_init()
567 /* manual power down post-PLL */ in inno_hdmi_phy_rk3228_init()
577 u32 m, v; in inno_hdmi_phy_rk3228_power_on() local
582 /* Power down Post-PLL */ in inno_hdmi_phy_rk3228_power_on()
586 /* Post-PLL update */ in inno_hdmi_phy_rk3228_power_on()
587 m = POST_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3228_power_on()
588 v = POST_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_power_on()
589 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
591 m = POST_PLL_FB_DIV_8_MASK; in inno_hdmi_phy_rk3228_power_on()
592 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); in inno_hdmi_phy_rk3228_power_on()
593 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
594 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
596 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
597 /* Disable Post-PLL post divider */ in inno_hdmi_phy_rk3228_power_on()
598 m = POST_PLL_POST_DIV_EN_MASK; in inno_hdmi_phy_rk3228_power_on()
600 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
602 /* Enable Post-PLL post divider */ in inno_hdmi_phy_rk3228_power_on()
603 m = POST_PLL_POST_DIV_EN_MASK; in inno_hdmi_phy_rk3228_power_on()
605 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
607 m = POST_PLL_POST_DIV_MASK; in inno_hdmi_phy_rk3228_power_on()
608 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); in inno_hdmi_phy_rk3228_power_on()
609 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
613 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
615 /* Power up Post-PLL */ in inno_hdmi_phy_rk3228_power_on()
629 printf("Post-PLL unlock\n"); in inno_hdmi_phy_rk3228_power_on()
630 return -ETIMEDOUT; in inno_hdmi_phy_rk3228_power_on()
637 if (cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3228_power_on()
653 /* Post-PLL power down */ in inno_hdmi_phy_rk3228_power_off()
662 u32 m, v; in inno_hdmi_phy_rk3228_pre_pll_update() local
664 /* Power down PRE-PLL */ in inno_hdmi_phy_rk3228_pre_pll_update()
667 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
668 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | in inno_hdmi_phy_rk3228_pre_pll_update()
669 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_pre_pll_update()
670 inno_update_bits(inno, 0xe2, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
672 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
674 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
675 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | in inno_hdmi_phy_rk3228_pre_pll_update()
676 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a); in inno_hdmi_phy_rk3228_pre_pll_update()
677 inno_update_bits(inno, 0xe4, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
679 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
680 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3228_pre_pll_update()
681 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d); in inno_hdmi_phy_rk3228_pre_pll_update()
682 inno_update_bits(inno, 0xe5, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
684 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | in inno_hdmi_phy_rk3228_pre_pll_update()
686 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3228_pre_pll_update()
687 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3228_pre_pll_update()
688 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b); in inno_hdmi_phy_rk3228_pre_pll_update()
689 inno_update_bits(inno, 0xe6, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
691 /* Power up PRE-PLL */ in inno_hdmi_phy_rk3228_pre_pll_update()
694 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3228_pre_pll_update()
698 printf("Pre-PLL unlock\n"); in inno_hdmi_phy_rk3228_pre_pll_update()
699 return -ETIMEDOUT; in inno_hdmi_phy_rk3228_pre_pll_update()
712 * Use phy internal register control in inno_hdmi_phy_rk3328_init()
731 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3328_power_on()
733 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
735 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
738 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
740 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
746 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); in inno_hdmi_phy_rk3328_power_on()
749 * 00 - 340mV in inno_hdmi_phy_rk3328_power_on()
750 * 01 - 280mV in inno_hdmi_phy_rk3328_power_on()
751 * 10 - 260mV in inno_hdmi_phy_rk3328_power_on()
752 * 11 - 240mV in inno_hdmi_phy_rk3328_power_on()
760 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3328_power_on()
767 } else if (phy_cfg->tmdsclock > 165000000) { in inno_hdmi_phy_rk3328_power_on()
781 val = 47520000000UL / phy_cfg->tmdsclock; in inno_hdmi_phy_rk3328_power_on()
798 printf("HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3328_power_on()
799 return -ETIMEDOUT; in inno_hdmi_phy_rk3328_power_on()
801 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3328_power_on()
827 /* Configure pre-pll */ in inno_hdmi_phy_rk3328_pre_pll_update()
828 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3328_pre_pll_update()
829 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3328_pre_pll_update()
830 if (cfg->fracdiv) in inno_hdmi_phy_rk3328_pre_pll_update()
831 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3328_pre_pll_update()
833 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; in inno_hdmi_phy_rk3328_pre_pll_update()
835 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3328_pre_pll_update()
836 val = (cfg->pclk_div_a & 0x1f) | in inno_hdmi_phy_rk3328_pre_pll_update()
837 ((cfg->pclk_div_b & 3) << 5); in inno_hdmi_phy_rk3328_pre_pll_update()
839 val = (cfg->pclk_div_d & 0x1f) | in inno_hdmi_phy_rk3328_pre_pll_update()
840 ((cfg->pclk_div_c & 3) << 5); in inno_hdmi_phy_rk3328_pre_pll_update()
842 val = ((cfg->tmds_div_a & 3) << 4) | in inno_hdmi_phy_rk3328_pre_pll_update()
843 ((cfg->tmds_div_b & 3) << 2) | in inno_hdmi_phy_rk3328_pre_pll_update()
844 (cfg->tmds_div_c & 3); in inno_hdmi_phy_rk3328_pre_pll_update()
847 if (cfg->fracdiv) { in inno_hdmi_phy_rk3328_pre_pll_update()
848 val = cfg->fracdiv & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
850 val = (cfg->fracdiv >> 8) & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
852 val = (cfg->fracdiv >> 16) & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
870 printf("Pre-PLL unlock\n"); in inno_hdmi_phy_rk3328_pre_pll_update()
871 return -ETIMEDOUT; in inno_hdmi_phy_rk3328_pre_pll_update()
907 inno->pixclock = rate; in inno_hdmi_3328_phy_pll_recalc_rate()
919 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_rk3528_power_on()
924 val = cfg->prediv; in inno_hdmi_phy_rk3528_power_on()
927 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3528_power_on()
931 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3528_power_on()
936 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3528_power_on()
938 val = (cfg->fbdiv >> 8) & BIT(0); in inno_hdmi_phy_rk3528_power_on()
942 val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1]; in inno_hdmi_phy_rk3528_power_on()
946 val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1]; in inno_hdmi_phy_rk3528_power_on()
950 inno_write(inno, 0xb5, phy_cfg->regs[2]); in inno_hdmi_phy_rk3528_power_on()
951 inno_write(inno, 0xb6, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
952 inno_write(inno, 0xb7, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
953 inno_write(inno, 0xb8, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
955 /* pre-emphasis */ in inno_hdmi_phy_rk3528_power_on()
956 inno_write(inno, 0xbb, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
957 inno_write(inno, 0xbc, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
958 inno_write(inno, 0xbd, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
974 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3528_power_on()
975 return -ETIMEDOUT; in inno_hdmi_phy_rk3528_power_on()
979 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3528_power_on()
1001 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3528_power_on()
1007 /* Enable PHY IRQ */ in inno_hdmi_phy_rk3528_power_on()
1024 /* Disable PHY IRQ */ in inno_hdmi_phy_rk3528_power_off()
1032 * Use phy internal register control in inno_hdmi_phy_rk3528_init()
1049 /* Configure pre-pll */ in inno_hdmi_phy_rk3528_pre_pll_update()
1050 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3528_pre_pll_update()
1051 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3528_pre_pll_update()
1052 if (cfg->fracdiv) in inno_hdmi_phy_rk3528_pre_pll_update()
1053 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3528_pre_pll_update()
1055 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; in inno_hdmi_phy_rk3528_pre_pll_update()
1057 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3528_pre_pll_update()
1058 val = (cfg->pclk_div_a & 0x1f) | in inno_hdmi_phy_rk3528_pre_pll_update()
1059 ((cfg->pclk_div_b & 3) << 5); in inno_hdmi_phy_rk3528_pre_pll_update()
1061 val = (cfg->pclk_div_d & 0x1f) | in inno_hdmi_phy_rk3528_pre_pll_update()
1062 ((cfg->pclk_div_c & 3) << 5); in inno_hdmi_phy_rk3528_pre_pll_update()
1064 val = ((cfg->tmds_div_a & 3) << 4) | in inno_hdmi_phy_rk3528_pre_pll_update()
1065 ((cfg->tmds_div_b & 3) << 2) | in inno_hdmi_phy_rk3528_pre_pll_update()
1066 (cfg->tmds_div_c & 3); in inno_hdmi_phy_rk3528_pre_pll_update()
1069 if (cfg->fracdiv) { in inno_hdmi_phy_rk3528_pre_pll_update()
1070 val = cfg->fracdiv & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1072 val = (cfg->fracdiv >> 8) & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1074 val = (cfg->fracdiv >> 16) & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1089 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3528_pre_pll_update()
1090 return -ETIMEDOUT; in inno_hdmi_phy_rk3528_pre_pll_update()
1127 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1129 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1157 * The last set of phy cfg is used to indicate whether in inno_hdmi_update_phy_table()
1158 * there is no more phy cfg data. in inno_hdmi_update_phy_table()
1210 { .compatible = "rockchip,rk3228-hdmi-phy",
1213 { .compatible = "rockchip,rk3328-hdmi-phy",
1216 { .compatible = "rockchip,rk3528-hdmi-phy",
1222 static int inno_hdmi_phy_init(struct rockchip_phy *phy) in inno_hdmi_phy_init() argument
1225 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_init()
1227 struct udevice *dev = phy->dev; in inno_hdmi_phy_init()
1228 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_init()
1236 inno->regs = (void *)RK3528_HDMIPHY_BASE; in inno_hdmi_phy_init()
1238 inno->regs = dev_read_addr_ptr(dev); in inno_hdmi_phy_init()
1239 inno->node = dev->node; in inno_hdmi_phy_init()
1241 if (!inno->regs) { in inno_hdmi_phy_init()
1242 printf("%s: failed to get phy address\n", __func__); in inno_hdmi_phy_init()
1243 return -ENOMEM; in inno_hdmi_phy_init()
1247 name = "rockchip,rk3528-hdmi-phy"; in inno_hdmi_phy_init()
1253 inno->plat_data = inno_hdmi_phy_of_match[i].data; in inno_hdmi_phy_init()
1259 dev_read_prop(dev, "rockchip,phy-table", &val); in inno_hdmi_phy_init()
1263 printf("Invalid phy cfg table format!\n"); in inno_hdmi_phy_init()
1264 return -EINVAL; in inno_hdmi_phy_init()
1269 printf("kmalloc phy table failed\n"); in inno_hdmi_phy_init()
1270 return -ENOMEM; in inno_hdmi_phy_init()
1274 /* Effective phy cfg data and the end of phy cfg table */ in inno_hdmi_phy_init()
1275 inno->phy_cfg = malloc(val + PHY_TAB_LEN); in inno_hdmi_phy_init()
1276 if (!inno->phy_cfg) { in inno_hdmi_phy_init()
1278 return -ENOMEM; in inno_hdmi_phy_init()
1281 dev_read_u32_array(dev, "rockchip,phy-table", in inno_hdmi_phy_init()
1284 inno->phy_cfg, in inno_hdmi_phy_init()
1292 printf("use default hdmi phy table\n"); in inno_hdmi_phy_init()
1299 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_init()
1300 return -EINVAL; in inno_hdmi_phy_init()
1302 if (inno->plat_data->ops->init) in inno_hdmi_phy_init()
1303 inno->plat_data->ops->init(inno); in inno_hdmi_phy_init()
1308 static unsigned long inno_hdmi_phy_set_pll(struct rockchip_phy *phy, in inno_hdmi_phy_set_pll() argument
1312 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_set_pll()
1314 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_set_pll()
1328 inno_hdmi_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) in inno_hdmi_phy_set_bus_width() argument
1331 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_set_bus_width()
1333 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_set_bus_width()
1336 inno->bus_width = bus_width; in inno_hdmi_phy_set_bus_width()
1342 inno_hdmi_phy_clk_round_rate(struct rockchip_phy *phy, unsigned long rate) in inno_hdmi_phy_clk_round_rate() argument
1345 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_clk_round_rate()
1347 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_clk_round_rate()
1353 for (; cfg->pixclock != ~0UL; cfg++) in inno_hdmi_phy_clk_round_rate()
1354 if (cfg->pixclock == rate) in inno_hdmi_phy_clk_round_rate()
1359 * rk3228 does not support non-zero fracdiv in inno_hdmi_phy_clk_round_rate()
1361 if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_clk_round_rate()
1362 cfg->fracdiv) || cfg->pixclock > 600000000) in inno_hdmi_phy_clk_round_rate()
1363 return -EINVAL; in inno_hdmi_phy_clk_round_rate()
1366 * If there is no dts phy cfg table, use default phy cfg table. in inno_hdmi_phy_clk_round_rate()
1370 if (!inno->phy_cfg) in inno_hdmi_phy_clk_round_rate()
1371 return cfg->pixclock; in inno_hdmi_phy_clk_round_rate()
1373 /* Check if tmds clock is out of dts phy config's range. */ in inno_hdmi_phy_clk_round_rate()
1374 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { in inno_hdmi_phy_clk_round_rate()
1375 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) in inno_hdmi_phy_clk_round_rate()
1379 if (inno->phy_cfg[i].tmdsclock == ~0UL) in inno_hdmi_phy_clk_round_rate()
1380 return -EINVAL; in inno_hdmi_phy_clk_round_rate()
1382 return cfg->pixclock; in inno_hdmi_phy_clk_round_rate()
1400 .compatible = "rockchip,rk3328-hdmi-phy",
1404 .compatible = "rockchip,rk3228-hdmi-phy",
1408 .compatible = "rockchip,rk3528-hdmi-phy",
1422 state->conn_state.connector->phy = &inno_hdmi_phy_driver_data; in inno_spl_hdmi_phy_probe()
1423 state->conn_state.connector->phy->data = (void *)inno; in inno_spl_hdmi_phy_probe()
1430 struct rockchip_phy *phy = in inno_hdmi_phy_probe() local
1433 inno->dev = dev; in inno_hdmi_phy_probe()
1434 phy->dev = dev; in inno_hdmi_phy_probe()
1437 dev->driver_data = (ulong)&inno_hdmi_phy_driver_data; in inno_hdmi_phy_probe()
1438 phy = &inno_hdmi_phy_driver_data; in inno_hdmi_phy_probe()
1450 subnode = ofnode_find_subnode(parent->node, "clk-port"); in rockchip_inno_phy_hdmi_bind()
1452 printf("%s: no subnode for %s\n", __func__, parent->name); in rockchip_inno_phy_hdmi_bind()
1453 return -ENXIO; in rockchip_inno_phy_hdmi_bind()
1458 printf("%s: clk-port cannot bind its driver\n", __func__); in rockchip_inno_phy_hdmi_bind()
1479 struct clk_inno_hdmi *priv = dev_get_priv(clk->dev); in inno_hdmi_clk_get_rate()
1481 return priv->rate; in inno_hdmi_clk_get_rate()
1486 struct clk_inno_hdmi *priv = dev_get_priv(clk->dev); in inno_hdmi_clk_set_rate()
1497 priv->rate = g_inno->pixclock; in inno_hdmi_clk_set_rate()
1499 return priv->rate; in inno_hdmi_clk_set_rate()