142 #define PHYREG(x)		((x) + 0x0c00)  macro
143 #define MIPI_PHY_REG0		PHYREG(0x0000)
146 #define MIPI_PHY_REG1		PHYREG(0x0004)
151 #define MIPI_PHY_REG3		PHYREG(0x000c)
156 #define MIPI_PHY_REG4		PHYREG(0x0010)
159 #define MIPI_PHY_REG5		PHYREG(0x0014)
160 #define MIPI_PHY_REG6		PHYREG(0x0018)
161 #define MIPI_PHY_REG7		PHYREG(0x001c)
162 #define MIPI_PHY_REG9		PHYREG(0x0024)
163 #define MIPI_PHY_REG20		PHYREG(0x0080)
165 #define MIPI_PHY_MAX_REGISTER	PHYREG(0x0348)
435 		dsi_update_bits(dsi, PHYREG(offset + THS_SETTLE_OFFSET),  in rk618_dsi_phy_power_on()
446 		dsi_update_bits(dsi, PHYREG(offset + TLPX_OFFSET),  in rk618_dsi_phy_power_on()
461 		dsi_update_bits(dsi, PHYREG(offset + THS_PREPARE_OFFSET),  in rk618_dsi_phy_power_on()
464 		dsi_update_bits(dsi, PHYREG(offset + THS_ZERO_OFFSET),  in rk618_dsi_phy_power_on()
468 		dsi_update_bits(dsi, PHYREG(offset + THS_TRAIL_OFFSET),  in rk618_dsi_phy_power_on()
478 		dsi_update_bits(dsi, PHYREG(offset + THS_EXIT_OFFSET),  in rk618_dsi_phy_power_on()
487 		dsi_update_bits(dsi, PHYREG(offset + TCLK_POST_OFFSET),  in rk618_dsi_phy_power_on()
495 		dsi_update_bits(dsi, PHYREG(offset + TWAKUP_HI_OFFSET),  in rk618_dsi_phy_power_on()
497 		dsi_update_bits(dsi, PHYREG(offset + TWAKUP_LO_OFFSET),  in rk618_dsi_phy_power_on()
507 		dsi_update_bits(dsi, PHYREG(offset + TCLK_PRE_OFFSET),  in rk618_dsi_phy_power_on()
517 		dsi_update_bits(dsi, PHYREG(offset + TTA_GO_OFFSET),  in rk618_dsi_phy_power_on()
527 		dsi_update_bits(dsi, PHYREG(offset + TTA_SURE_OFFSET),  in rk618_dsi_phy_power_on()
539 		dsi_update_bits(dsi, PHYREG(offset + TTA_WAIT_OFFSET),  in rk618_dsi_phy_power_on()