Lines Matching +full:hs +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <dm/device-internal.h>
141 /* phy registers */
221 struct mipi_dphy phy; member
258 (cond) ? 0 : -ETIMEDOUT; \
263 return rk618_i2c_write(dsi->parent, reg, val); in dsi_write()
270 rk618_i2c_read(dsi->parent, reg, &val); in dsi_read()
296 const struct drm_display_mode *mode = &dsi->mode; in rk618_dsi_set_hs_clk()
297 struct mipi_dphy *phy = &dsi->phy; in rk618_dsi_set_hs_clk() local
302 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); in rk618_dsi_set_hs_clk()
306 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in rk618_dsi_set_hs_clk()
307 unsigned int lanes = dsi->lanes; in rk618_dsi_set_hs_clk()
310 bandwidth = (u64)mode->clock * 1000 * bpp; in rk618_dsi_set_hs_clk()
325 fref = clk_get_rate(&dsi->parent->clkin); in rk618_dsi_set_hs_clk()
347 delta = abs(fout - tmp); in rk618_dsi_set_hs_clk()
349 phy->rate = tmp; in rk618_dsi_set_hs_clk()
350 phy->prediv = prediv; in rk618_dsi_set_hs_clk()
351 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
354 phy->rate = tmp; in rk618_dsi_set_hs_clk()
355 phy->prediv = prediv; in rk618_dsi_set_hs_clk()
356 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
371 struct mipi_dphy *phy = &dsi->phy; in rk618_dsi_phy_power_on() local
395 Ttxbyteclkhs = div_u64(PSEC_PER_SEC, phy->rate / 8); in rk618_dsi_phy_power_on()
396 UI = Ttxddrclkhs = div_u64(PSEC_PER_SEC, phy->rate); in rk618_dsi_phy_power_on()
400 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) | in rk618_dsi_phy_power_on()
401 REG_PREDIV(phy->prediv)); in rk618_dsi_phy_power_on()
403 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv)); in rk618_dsi_phy_power_on()
407 LANE_EN_CK | GENMASK(dsi->lanes - 1 + 2, 2)); in rk618_dsi_phy_power_on()
422 if (phy->rate < 800000000) in rk618_dsi_phy_power_on()
428 if (phy->rate <= timing_table[index].rate) in rk618_dsi_phy_power_on()
432 --index; in rk618_dsi_phy_power_on()
440 * The value of counter for HS Tlpx Time in rk618_dsi_phy_power_on()
450 * The value of counter for HS Ths-prepare in rk618_dsi_phy_power_on()
451 * For clock lane, Ths-prepare(38ns~95ns) in rk618_dsi_phy_power_on()
452 * For data lane, Ths-prepare(40ns+4UI~85ns+6UI) in rk618_dsi_phy_power_on()
453 * Ths-prepare = Ttxddrclkhs * value in rk618_dsi_phy_power_on()
473 * The value of counter for HS Ths-exit in rk618_dsi_phy_power_on()
474 * Ths-exit = Tpin_txbyteclkhs * value in rk618_dsi_phy_power_on()
482 * The value of counter for HS Tclk-post in rk618_dsi_phy_power_on()
483 * Tclk-post = Ttxbyteclkhs * value in rk618_dsi_phy_power_on()
491 * The value of counter for HS Twakup in rk618_dsi_phy_power_on()
501 * The value of counter for HS Tclk-pre in rk618_dsi_phy_power_on()
502 * Tclk-pre for clock lane in rk618_dsi_phy_power_on()
503 * Tclk-pre = Tpin_txbyteclkhs * value in rk618_dsi_phy_power_on()
511 * The value of counter for HS Tta-go in rk618_dsi_phy_power_on()
512 * Tta-go for turnaround in rk618_dsi_phy_power_on()
513 * Tta-go = Ttxclkesc * value in rk618_dsi_phy_power_on()
521 * The value of counter for HS Tta-sure in rk618_dsi_phy_power_on()
522 * Tta-sure for turnaround in rk618_dsi_phy_power_on()
523 * Tta-sure = Ttxclkesc * value in rk618_dsi_phy_power_on()
531 * The value of counter for HS Tta-wait in rk618_dsi_phy_power_on()
532 * Tta-wait for turnaround in rk618_dsi_phy_power_on()
535 * Tta-wait = Ttxclkesc * value in rk618_dsi_phy_power_on()
546 struct drm_display_mode *mode = &dsi->mode; in rk618_dsi_pre_enable()
559 esc_clk_div = DIV_ROUND_UP(dsi->phy.rate >> 3, 20000000); in rk618_dsi_pre_enable()
560 txclkesc = dsi->phy.rate >> 3 / esc_clk_div; in rk618_dsi_pre_enable()
565 value = DPI_VID(dsi->channel); in rk618_dsi_pre_enable()
567 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in rk618_dsi_pre_enable()
569 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in rk618_dsi_pre_enable()
572 switch (dsi->format) { in rk618_dsi_pre_enable()
592 value = GEN_VID_RX(dsi->channel) | EN_CRC_RX | EN_ECC_RX | EN_BTA; in rk618_dsi_pre_enable()
594 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) in rk618_dsi_pre_enable()
602 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) in rk618_dsi_pre_enable()
605 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) in rk618_dsi_pre_enable()
608 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) in rk618_dsi_pre_enable()
610 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in rk618_dsi_pre_enable()
618 dsi_write(dsi, DSI_VID_PKT_CFG, VID_PKT_SIZE(mode->hdisplay)); in rk618_dsi_pre_enable()
623 hsw = mode->hsync_end - mode->hsync_start; in rk618_dsi_pre_enable()
624 hbp = mode->htotal - mode->hsync_end; in rk618_dsi_pre_enable()
625 vsw = mode->vsync_end - mode->vsync_start; in rk618_dsi_pre_enable()
626 vfp = mode->vsync_start - mode->vdisplay; in rk618_dsi_pre_enable()
627 vbp = mode->vtotal - mode->vsync_end; in rk618_dsi_pre_enable()
630 lanebyteclk = (dsi->phy.rate >> 3) / USEC_PER_SEC; in rk618_dsi_pre_enable()
631 dpipclk = mode->clock / USEC_PER_MSEC; in rk618_dsi_pre_enable()
632 hline_time = DIV_ROUND_UP(mode->htotal * lanebyteclk, dpipclk); in rk618_dsi_pre_enable()
640 V_ACTIVE_LINES(mode->vdisplay) | VFP_LINES(vfp) | in rk618_dsi_pre_enable()
643 /* D-PHY interface configuration */ in rk618_dsi_pre_enable()
644 value = N_LANES(dsi->lanes - 1) | PHY_STOP_WAIT_TIME(0x20); in rk618_dsi_pre_enable()
647 /* D-PHY timing configuration */ in rk618_dsi_pre_enable()
651 /* enables the D-PHY Clock Lane Module */ in rk618_dsi_pre_enable()
659 /* wait for the PHY to acquire lock */ in rk618_dsi_pre_enable()
663 dev_err(dsi->dev, "PHY is not locked\n"); in rk618_dsi_pre_enable()
671 dev_err(dsi->dev, "lane module is not in stop state\n"); in rk618_dsi_pre_enable()
682 /* controls the D-PHY PPI txrequestclkhs signal */ in rk618_dsi_enable()
692 printf("final DSI-Link bandwidth: %lu x %d Mbps\n", in rk618_dsi_enable()
693 dsi->phy.rate / USEC_PER_SEC, dsi->lanes); in rk618_dsi_enable()
716 struct rk618_dsi *dsi = dev_get_priv(bridge->dev); in rk618_dsi_bridge_pre_enable()
723 struct rk618_dsi *dsi = dev_get_priv(bridge->dev); in rk618_dsi_bridge_enable()
730 struct rk618_dsi *dsi = dev_get_priv(bridge->dev); in rk618_dsi_bridge_post_disable()
737 struct rk618_dsi *dsi = dev_get_priv(bridge->dev); in rk618_dsi_bridge_disable()
745 struct rk618_dsi *dsi = dev_get_priv(bridge->dev); in rk618_dsi_bridge_mode_set()
747 memcpy(&dsi->mode, mode, sizeof(*mode)); in rk618_dsi_bridge_mode_set()
765 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in rk618_dsi_transfer()
771 switch (msg->type) { in rk618_dsi_transfer()
774 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
779 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
784 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
789 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
795 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
800 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
805 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
810 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
815 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
820 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
825 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
830 msg->flags & MIPI_DSI_MSG_USE_LPM ? in rk618_dsi_transfer()
834 return -EINVAL; in rk618_dsi_transfer()
840 dev_err(dsi->dev, "failed to create packet: %d\n", ret); in rk618_dsi_transfer()
850 dev_err(dsi->dev, "Write payload FIFO is full\n"); in rk618_dsi_transfer()
857 packet.payload_length -= 4; in rk618_dsi_transfer()
878 dev_err(dsi->dev, "Command FIFO is full\n"); in rk618_dsi_transfer()
890 dev_err(dsi->dev, "Write payload FIFO is not empty\n"); in rk618_dsi_transfer()
894 if (msg->rx_len) { in rk618_dsi_transfer()
895 u8 *payload = msg->rx_buf; in rk618_dsi_transfer()
902 dev_err(dsi->dev, in rk618_dsi_transfer()
908 for (length = msg->rx_len; length; length -= 4) { in rk618_dsi_transfer()
914 dev_err(dsi->dev, in rk618_dsi_transfer()
951 dsi->dev = dev; in rk618_dsi_probe()
952 dsi->parent = dev_get_priv(dev->parent); in rk618_dsi_probe()
954 ret = device_probe(dev->parent); in rk618_dsi_probe()
958 bridge->dev = dev; in rk618_dsi_probe()
973 .compatible = "rockchip,rk618-dsi",
982 struct rk618_dsi *dsi = dev_get_priv(host->dev); in rk618_dsi_host_transfer()
990 struct rk618_dsi *dsi = dev_get_priv(host->dev); in rk618_dsi_host_attach()
992 if (device->lanes < 1 || device->lanes > 4) in rk618_dsi_host_attach()
993 return -EINVAL; in rk618_dsi_host_attach()
995 dsi->lanes = device->lanes; in rk618_dsi_host_attach()
996 dsi->channel = device->channel; in rk618_dsi_host_attach()
997 dsi->format = device->format; in rk618_dsi_host_attach()
998 dsi->mode_flags = device->mode_flags; in rk618_dsi_host_attach()
1012 host->dev = dev; in rk618_dsi_bind()
1013 host->ops = &rk618_dsi_host_ops; in rk618_dsi_bind()
1020 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); in rk618_dsi_child_post_bind()
1024 sprintf(name, "%s.%d", host->dev->name, device->channel); in rk618_dsi_child_post_bind()
1027 device->dev = dev; in rk618_dsi_child_post_bind()
1028 device->host = host; in rk618_dsi_child_post_bind()
1029 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); in rk618_dsi_child_post_bind()
1030 device->format = dev_read_u32_default(dev, "dsi,format", in rk618_dsi_child_post_bind()
1032 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", in rk618_dsi_child_post_bind()
1038 device->channel = dev_read_u32_default(dev, "reg", 0); in rk618_dsi_child_post_bind()