Lines Matching +full:0 +full:x77
28 #define GRF_HDPTX_CON0 0x00
33 #define GRF_HDPTX_STATUS 0x80
37 #define HDPTX_O_SB_RDY BIT(0)
39 #define CMN_REG0000 0x0000
40 #define CMN_REG0001 0x0004
41 #define CMN_REG0002 0x0008
42 #define CMN_REG0003 0x000C
43 #define CMN_REG0004 0x0010
44 #define CMN_REG0005 0x0014
45 #define CMN_REG0006 0x0018
46 #define CMN_REG0007 0x001C
47 #define CMN_REG0008 0x0020
52 #define CMN_REG0009 0x0024
53 #define CMN_REG000A 0x0028
54 #define CMN_REG000B 0x002C
55 #define CMN_REG000C 0x0030
56 #define CMN_REG000D 0x0034
57 #define CMN_REG000E 0x0038
58 #define CMN_REG000F 0x003C
59 #define CMN_REG0010 0x0040
60 #define CMN_REG0011 0x0044
61 #define CMN_REG0012 0x0048
62 #define CMN_REG0013 0x004C
63 #define CMN_REG0014 0x0050
64 #define CMN_REG0015 0x0054
65 #define CMN_REG0016 0x0058
66 #define CMN_REG0017 0x005C
67 #define CMN_REG0018 0x0060
68 #define CMN_REG0019 0x0064
69 #define CMN_REG001A 0x0068
70 #define CMN_REG001B 0x006C
71 #define CMN_REG001C 0x0070
72 #define CMN_REG001D 0x0074
73 #define CMN_REG001E 0x0078
76 #define LCPLL_100M_CLK_EN_MASK BIT(0)
77 #define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0)
78 #define CMN_REG001F 0x007C
79 #define CMN_REG0020 0x0080
80 #define CMN_REG0021 0x0084
81 #define CMN_REG0022 0x0088
82 #define CMN_REG0023 0x008C
83 #define CMN_REG0024 0x0090
84 #define CMN_REG0025 0x0094
86 #define CMN_REG0026 0x0098
87 #define CMN_REG0027 0x009C
88 #define CMN_REG0028 0x00A0
90 #define LCPLL_SDC_FRAC_RSTN BIT(0)
91 #define CMN_REG0029 0x00A4
92 #define CMN_REG002A 0x00A8
93 #define CMN_REG002B 0x00AC
94 #define CMN_REG002C 0x00B0
95 #define CMN_REG002D 0x00B4
98 #define CMN_REG002E 0x00B8
99 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
100 #define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0)
101 #define CMN_REG002F 0x00BC
104 #define LCPLL_SDC_NDIV_RSTN BIT(0)
105 #define CMN_REG0030 0x00C0
106 #define CMN_REG0031 0x00C4
107 #define CMN_REG0032 0x00C8
108 #define CMN_REG0033 0x00CC
109 #define CMN_REG0034 0x00D0
110 #define CMN_REG0035 0x00D4
111 #define CMN_REG0036 0x00D8
112 #define CMN_REG0037 0x00DC
113 #define CMN_REG0038 0x00E0
114 #define CMN_REG0039 0x00E4
115 #define CMN_REG003A 0x00E8
116 #define CMN_REG003B 0x00EC
117 #define CMN_REG003C 0x00F0
118 #define CMN_REG003D 0x00F4
120 #define CMN_REG003E 0x00F8
121 #define CMN_REG003F 0x00FC
122 #define CMN_REG0040 0x0100
123 #define CMN_REG0041 0x0104
124 #define CMN_REG0042 0x0108
125 #define CMN_REG0043 0x010C
126 #define CMN_REG0044 0x0110
127 #define CMN_REG0045 0x0114
128 #define CMN_REG0046 0x0118
129 #define CMN_REG0047 0x011C
130 #define CMN_REG0048 0x0120
131 #define CMN_REG0049 0x0124
132 #define CMN_REG004A 0x0128
133 #define CMN_REG004B 0x012C
134 #define CMN_REG004C 0x0130
135 #define CMN_REG004D 0x0134
136 #define CMN_REG004E 0x0138
138 #define CMN_REG004F 0x013C
139 #define CMN_REG0050 0x0140
140 #define CMN_REG0051 0x0144
141 #define CMN_REG0052 0x0148
142 #define CMN_REG0053 0x014C
143 #define CMN_REG0054 0x0150
144 #define CMN_REG0055 0x0154
145 #define CMN_REG0056 0x0158
146 #define CMN_REG0057 0x015C
147 #define CMN_REG0058 0x0160
148 #define CMN_REG0059 0x0164
149 #define CMN_REG005A 0x0168
150 #define CMN_REG005B 0x016C
151 #define CMN_REG005C 0x0170
153 #define CMN_REG005D 0x0174
154 #define CMN_REG005E 0x0178
160 #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
161 #define CMN_REG005F 0x017C
162 #define CMN_REG0060 0x0180
163 #define CMN_REG0061 0x0184
164 #define CMN_REG0062 0x0188
165 #define CMN_REG0063 0x018C
166 #define CMN_REG0064 0x0190
169 #define CMN_REG0065 0x0194
170 #define CMN_REG0066 0x0198
171 #define CMN_REG0067 0x019C
172 #define CMN_REG0068 0x01A0
173 #define CMN_REG0069 0x01A4
174 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
175 #define ROPLL_SDC_N_RBR(x) UPDATE(x, 2, 0)
176 #define CMN_REG006A 0x01A8
177 #define CMN_REG006B 0x01AC
178 #define CMN_REG006C 0x01B0
179 #define CMN_REG006D 0x01B4
180 #define CMN_REG006E 0x01B8
181 #define CMN_REG006F 0x01BC
182 #define CMN_REG0070 0x01C0
183 #define CMN_REG0071 0x01C4
184 #define CMN_REG0072 0x01C8
185 #define CMN_REG0073 0x01CC
186 #define CMN_REG0074 0x01D0
188 #define ROPLL_SSC_EN BIT(0)
189 #define CMN_REG0075 0x01D4
190 #define CMN_REG0076 0x01D8
191 #define CMN_REG0077 0x01DC
192 #define CMN_REG0078 0x01E0
193 #define CMN_REG0079 0x01E4
194 #define CMN_REG007A 0x01E8
195 #define CMN_REG007B 0x01EC
196 #define CMN_REG007C 0x01F0
197 #define CMN_REG007D 0x01F4
198 #define CMN_REG007E 0x01F8
199 #define CMN_REG007F 0x01FC
200 #define CMN_REG0080 0x0200
201 #define CMN_REG0081 0x0204
203 #define PLL_CD_HSCLK_EAST_EN BIT(0)
204 #define CMN_REG0082 0x0208
205 #define CMN_REG0083 0x020C
206 #define CMN_REG0084 0x0210
207 #define CMN_REG0085 0x0214
208 #define CMN_REG0086 0x0218
213 #define PLL_PCG_CLK_EN BIT(0)
214 #define CMN_REG0087 0x021C
217 #define CMN_REG0088 0x0220
218 #define CMN_REG0089 0x0224
220 #define CMN_REG008A 0x0228
221 #define CMN_REG008B 0x022C
222 #define CMN_REG008C 0x0230
223 #define CMN_REG008D 0x0234
224 #define CMN_REG008E 0x0238
225 #define CMN_REG008F 0x023C
226 #define CMN_REG0090 0x0240
227 #define CMN_REG0091 0x0244
228 #define CMN_REG0092 0x0248
229 #define CMN_REG0093 0x024C
230 #define CMN_REG0094 0x0250
231 #define CMN_REG0095 0x0254
232 #define CMN_REG0096 0x0258
233 #define CMN_REG0097 0x025C
236 #define LCPLL_REF 0
237 #define CMN_REG0098 0x0260
238 #define CMN_REG0099 0x0264
241 #define CMN_REG009A 0x0268
242 #define HS_SPEED_SEL BIT(0)
243 #define DIV_10_CLOCK BIT(0)
244 #define CMN_REG009B 0x026C
247 #define LINK_SYMBOL_CLOCK1_2 0
248 #define CMN_REG009C 0x0270
249 #define CMN_REG009D 0x0274
250 #define CMN_REG009E 0x0278
251 #define CMN_REG009F 0x027C
252 #define CMN_REG00A0 0x0280
253 #define CMN_REG00A1 0x0284
254 #define CMN_REG00A2 0x0288
255 #define CMN_REG00A3 0x028C
256 #define CMN_REG00AD 0x0290
257 #define CMN_REG00A5 0x0294
258 #define CMN_REG00A6 0x0298
259 #define CMN_REG00A7 0x029C
260 #define SB_REG0100 0x0400
261 #define SB_REG0101 0x0404
262 #define SB_REG0102 0x0408
267 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
268 #define ANA_SB_RXTERM_OFFSP(x) UPDATE(x, 3, 0)
269 #define SB_REG0103 0x040C
274 #define SB_RX_RESCAL_DONE_MASK BIT(0)
275 #define SB_RX_RESCAL_DONE(x) UPDATE(x, 0, 0)
276 #define SB_REG0104 0x0410
281 #define SB_REG0105 0x0414
286 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
287 #define ANA_SB_TX_HLVL_PROG(x) UPDATE(x, 2, 0)
288 #define SB_REG0106 0x0418
291 #define SB_REG0107 0x041C
292 #define SB_REG0108 0x0420
293 #define SB_REG0109 0x0424
294 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
295 #define ANA_SB_DMRX_AFC_DIV_RATIO(x) UPDATE(x, 2, 0)
296 #define SB_REG010A 0x0428
297 #define SB_REG010B 0x042C
298 #define SB_REG010C 0x0430
299 #define SB_REG010D 0x0434
300 #define SB_REG010E 0x0438
301 #define SB_REG010F 0x043C
310 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
311 #define ANA_SB_VREG_GAIN_CTRL(x) UPDATE(x, 3, 0)
312 #define SB_REG0110 0x0440
313 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
314 #define ANA_SB_VREG_REF_SEL(x) UPDATE(x, 0, 0)
315 #define SB_REG0111 0x0444
316 #define SB_REG0112 0x0448
317 #define SB_REG0113 0x044C
320 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
321 #define SB_RX_RTERM_CTRL(x) UPDATE(x, 3, 0)
322 #define SB_REG0114 0x0450
325 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
326 #define SB_TG_RXTERM_EN_DELAY_TIME(x) UPDATE(x, 2, 0)
327 #define SB_REG0115 0x0454
330 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
331 #define SB_TG_OSC_EN_DELAY_TIME(x) UPDATE(x, 2, 0)
332 #define SB_REG0116 0x0458
335 #define SB_REG0117 0x045C
336 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
337 #define FAST_PULSE_TIME(x) UPDATE(x, 3, 0)
338 #define SB_REG0118 0x0460
339 #define SB_REG0119 0x0464
340 #define SB_REG011A 0x0468
341 #define SB_REG011B 0x046C
344 #define SB_AFC_TOL_MASK GENMASK(3, 0)
345 #define SB_AFC_TOL(x) UPDATE(x, 3, 0)
346 #define SB_REG011C 0x0470
347 #define SB_REG011D 0x0474
348 #define SB_REG011E 0x0478
349 #define SB_REG011F 0x047C
354 #define SB_REG0120 0x0480
359 #define SB_REG0121 0x0484
360 #define SB_REG0122 0x0488
361 #define SB_REG0123 0x048C
366 #define SB_REG0124 0x0490
367 #define SB_REG0125 0x0494
368 #define SB_REG0126 0x0498
369 #define SB_REG0127 0x049C
370 #define SB_REG0128 0x04A0
371 #define SB_REG0129 0x04AD
372 #define LNTOP_REG0200 0x0800
376 #define LNTOP_REG0201 0x0804
377 #define LNTOP_REG0202 0x0808
378 #define LNTOP_REG0203 0x080C
379 #define LNTOP_REG0204 0x0810
380 #define LNTOP_REG0205 0x0814
381 #define LNTOP_REG0206 0x0818
382 #define DATA_BUS_WIDTH (0x3 << 1)
383 #define WIDTH_40BIT (0x3 << 1)
384 #define WIDTH_36BIT (0x2 << 1)
385 #define DATA_BUS_SEL BIT(0)
386 #define DATA_BUS_36_40 BIT(0)
387 #define LNTOP_REG0207 0x081C
388 #define LANE_EN 0xf
389 #define ALL_LANE_EN 0xf
390 #define LNTOP_REG0208 0x0820
391 #define LNTOP_REG0209 0x0824
392 #define LNTOP_REG020A 0x0828
393 #define LNTOP_REG020B 0x082C
394 #define LNTOP_REG020C 0x0830
395 #define LNTOP_REG020D 0x0834
396 #define LNTOP_REG020E 0x0838
397 #define LNTOP_REG020F 0x083C
398 #define LNTOP_REG0210 0x0840
399 #define LNTOP_REG0211 0x0844
400 #define LNTOP_REG0212 0x0848
401 #define LNTOP_REG0213 0x084C
402 #define LNTOP_REG0214 0x0850
403 #define LNTOP_REG0215 0x0854
404 #define LNTOP_REG0216 0x0858
405 #define LNTOP_REG0217 0x085C
406 #define LNTOP_REG0218 0x0860
407 #define LNTOP_REG0219 0x0864
408 #define LNTOP_REG021A 0x0868
409 #define LNTOP_REG021B 0x086C
410 #define LNTOP_REG021C 0x0870
411 #define LNTOP_REG021D 0x0874
412 #define LNTOP_REG021E 0x0878
413 #define LNTOP_REG021F 0x087C
414 #define LNTOP_REG0220 0x0880
415 #define LNTOP_REG0221 0x0884
416 #define LNTOP_REG0222 0x0888
417 #define LNTOP_REG0223 0x088C
418 #define LNTOP_REG0224 0x0890
419 #define LNTOP_REG0225 0x0894
420 #define LNTOP_REG0226 0x0898
421 #define LNTOP_REG0227 0x089C
422 #define LNTOP_REG0228 0x08A0
423 #define LNTOP_REG0229 0x08A4
424 #define LANE_REG0300 0x0C00
425 #define LANE_REG0301 0x0C04
426 #define LANE_REG0302 0x0C08
427 #define LANE_REG0303 0x0C0C
428 #define LANE_REG0304 0x0C10
429 #define LANE_REG0305 0x0C14
430 #define LANE_REG0306 0x0C18
431 #define LANE_REG0307 0x0C1C
432 #define LANE_REG0308 0x0C20
433 #define LANE_REG0309 0x0C24
434 #define LANE_REG030A 0x0C28
435 #define LANE_REG030B 0x0C2C
436 #define LANE_REG030C 0x0C30
437 #define LANE_REG030D 0x0C34
438 #define LANE_REG030E 0x0C38
439 #define LANE_REG030F 0x0C3C
440 #define LANE_REG0310 0x0C40
441 #define LANE_REG0311 0x0C44
442 #define LANE_REG0312 0x0C48
447 #define LANE_REG0313 0x0C4C
448 #define LANE_REG0314 0x0C50
449 #define LANE_REG0315 0x0C54
450 #define LANE_REG0316 0x0C58
451 #define LANE_REG0317 0x0C5C
452 #define LANE_REG0318 0x0C60
453 #define LANE_REG0319 0x0C64
454 #define LANE_REG031A 0x0C68
455 #define LANE_REG031B 0x0C6C
456 #define LANE_REG031C 0x0C70
457 #define LANE_REG031D 0x0C74
458 #define LANE_REG031E 0x0C78
459 #define LANE_REG031F 0x0C7C
460 #define LANE_REG0320 0x0C80
461 #define LANE_REG0321 0x0C84
462 #define LANE_REG0322 0x0C88
463 #define LANE_REG0323 0x0C8C
464 #define LANE_REG0324 0x0C90
465 #define LANE_REG0325 0x0C94
466 #define LANE_REG0326 0x0C98
467 #define LANE_REG0327 0x0C9C
468 #define LANE_REG0328 0x0CA0
469 #define LANE_REG0329 0x0CA4
470 #define LANE_REG032A 0x0CA8
471 #define LANE_REG032B 0x0CAC
472 #define LANE_REG032C 0x0CB0
473 #define LANE_REG032D 0x0CB4
474 #define LANE_REG0400 0x1000
475 #define LANE_REG0401 0x1004
476 #define LANE_REG0402 0x1008
477 #define LANE_REG0403 0x100C
478 #define LANE_REG0404 0x1010
479 #define LANE_REG0405 0x1014
480 #define LANE_REG0406 0x1018
481 #define LANE_REG0407 0x101C
482 #define LANE_REG0408 0x1020
483 #define LANE_REG0409 0x1024
484 #define LANE_REG040A 0x1028
485 #define LANE_REG040B 0x102C
486 #define LANE_REG040C 0x1030
487 #define LANE_REG040D 0x1034
488 #define LANE_REG040E 0x1038
489 #define LANE_REG040F 0x103C
490 #define LANE_REG0410 0x1040
491 #define LANE_REG0411 0x1044
492 #define LANE_REG0412 0x1048
497 #define LANE_REG0413 0x104C
498 #define LANE_REG0414 0x1050
499 #define LANE_REG0415 0x1054
500 #define LANE_REG0416 0x1058
501 #define LANE_REG0417 0x105C
502 #define LANE_REG0418 0x1060
503 #define LANE_REG0419 0x1064
504 #define LANE_REG041A 0x1068
505 #define LANE_REG041B 0x106C
506 #define LANE_REG041C 0x1070
507 #define LANE_REG041D 0x1074
508 #define LANE_REG041E 0x1078
509 #define LANE_REG041F 0x107C
510 #define LANE_REG0420 0x1080
511 #define LANE_REG0421 0x1084
512 #define LANE_REG0422 0x1088
513 #define LANE_REG0423 0x108C
514 #define LANE_REG0424 0x1090
515 #define LANE_REG0425 0x1094
516 #define LANE_REG0426 0x1098
517 #define LANE_REG0427 0x109C
518 #define LANE_REG0428 0x10A0
519 #define LANE_REG0429 0x10A4
520 #define LANE_REG042A 0x10A8
521 #define LANE_REG042B 0x10AC
522 #define LANE_REG042C 0x10B0
523 #define LANE_REG042D 0x10B4
524 #define LANE_REG0500 0x1400
525 #define LANE_REG0501 0x1404
526 #define LANE_REG0502 0x1408
527 #define LANE_REG0503 0x140C
528 #define LANE_REG0504 0x1410
529 #define LANE_REG0505 0x1414
530 #define LANE_REG0506 0x1418
531 #define LANE_REG0507 0x141C
532 #define LANE_REG0508 0x1420
533 #define LANE_REG0509 0x1424
534 #define LANE_REG050A 0x1428
535 #define LANE_REG050B 0x142C
536 #define LANE_REG050C 0x1430
537 #define LANE_REG050D 0x1434
538 #define LANE_REG050E 0x1438
539 #define LANE_REG050F 0x143C
540 #define LANE_REG0510 0x1440
541 #define LANE_REG0511 0x1444
542 #define LANE_REG0512 0x1448
547 #define LANE_REG0513 0x144C
548 #define LANE_REG0514 0x1450
549 #define LANE_REG0515 0x1454
550 #define LANE_REG0516 0x1458
551 #define LANE_REG0517 0x145C
552 #define LANE_REG0518 0x1460
553 #define LANE_REG0519 0x1464
554 #define LANE_REG051A 0x1468
555 #define LANE_REG051B 0x146C
556 #define LANE_REG051C 0x1470
557 #define LANE_REG051D 0x1474
558 #define LANE_REG051E 0x1478
559 #define LANE_REG051F 0x147C
560 #define LANE_REG0520 0x1480
561 #define LANE_REG0521 0x1484
562 #define LANE_REG0522 0x1488
563 #define LANE_REG0523 0x148C
564 #define LANE_REG0524 0x1490
565 #define LANE_REG0525 0x1494
566 #define LANE_REG0526 0x1498
567 #define LANE_REG0527 0x149C
568 #define LANE_REG0528 0x14A0
569 #define LANE_REG0529 0x14AD
570 #define LANE_REG052A 0x14A8
571 #define LANE_REG052B 0x14AC
572 #define LANE_REG052C 0x14B0
573 #define LANE_REG052D 0x14B4
574 #define LANE_REG0600 0x1800
575 #define LANE_REG0601 0x1804
576 #define LANE_REG0602 0x1808
577 #define LANE_REG0603 0x180C
578 #define LANE_REG0604 0x1810
579 #define LANE_REG0605 0x1814
580 #define LANE_REG0606 0x1818
581 #define LANE_REG0607 0x181C
582 #define LANE_REG0608 0x1820
583 #define LANE_REG0609 0x1824
584 #define LANE_REG060A 0x1828
585 #define LANE_REG060B 0x182C
586 #define LANE_REG060C 0x1830
587 #define LANE_REG060D 0x1834
588 #define LANE_REG060E 0x1838
589 #define LANE_REG060F 0x183C
590 #define LANE_REG0610 0x1840
591 #define LANE_REG0611 0x1844
592 #define LANE_REG0612 0x1848
597 #define LANE_REG0613 0x184C
598 #define LANE_REG0614 0x1850
599 #define LANE_REG0615 0x1854
600 #define LANE_REG0616 0x1858
601 #define LANE_REG0617 0x185C
602 #define LANE_REG0618 0x1860
603 #define LANE_REG0619 0x1864
604 #define LANE_REG061A 0x1868
605 #define LANE_REG061B 0x186C
606 #define LANE_REG061C 0x1870
607 #define LANE_REG061D 0x1874
608 #define LANE_REG061E 0x1878
609 #define LANE_REG061F 0x187C
610 #define LANE_REG0620 0x1880
611 #define LANE_REG0621 0x1884
612 #define LANE_REG0622 0x1888
613 #define LANE_REG0623 0x188C
614 #define LANE_REG0624 0x1890
615 #define LANE_REG0625 0x1894
616 #define LANE_REG0626 0x1898
617 #define LANE_REG0627 0x189C
618 #define LANE_REG0628 0x18A0
619 #define LANE_REG0629 0x18A4
620 #define LANE_REG062A 0x18A8
621 #define LANE_REG062B 0x18AC
622 #define LANE_REG062C 0x18B0
623 #define LANE_REG062D 0x18B4
626 #define DATA_RATE_MASK 0xFFFFFFF
727 { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
728 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0,
730 { 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1,
731 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0,
733 { 24000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
734 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0,
736 { 18000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
737 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0,
739 { 9000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 3, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
740 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0,
742 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
743 0, 0, 0, 0, 0, 0,
748 { 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
749 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
751 { 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
752 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
754 { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0,
755 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
757 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
758 0, 0, 0, 0,
763 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
764 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
766 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
767 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
769 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
770 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
772 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
773 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
775 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
776 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
778 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
779 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
781 { 1462500, 122, 122, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 1, 0, 1,
782 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
784 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
785 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
787 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
788 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
790 { 855000, 125, 125, 1, 1, 6, 1, 1, 1, 1, 1, 1, 1, 80, 1, 16, 2, 0,
791 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
793 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
794 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
796 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
797 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
799 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
800 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
802 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
803 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
805 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1,
806 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
808 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
809 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
811 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14,
812 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
814 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1,
815 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0,
817 { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
818 0, 0, 0, 0,
864 u32 val = 0; in hdptx_pre_power_up()
880 u32 val = 0; in hdptx_post_enable_lane()
891 hdptx_write(hdptx, LNTOP_REG0207, 0x07); in hdptx_post_enable_lane()
893 hdptx_write(hdptx, LNTOP_REG0207, 0x0f); in hdptx_post_enable_lane()
895 val = 0; in hdptx_post_enable_lane()
896 for (i = 0; i < 50; i++) { in hdptx_post_enable_lane()
911 return 0; in hdptx_post_enable_lane()
916 u32 val = 0; in hdptx_post_enable_pll()
930 val = 0; in hdptx_post_enable_pll()
931 for (i = 0; i < 50; i++) { in hdptx_post_enable_pll()
947 return 0; in hdptx_post_enable_pll()
958 unsigned long k = 0, lc, k_sub, lc_sub; in hdptx_phy_clk_pll_calc()
983 GENMASK(6, 0), in hdptx_phy_clk_pll_calc()
984 GENMASK(7, 0), in hdptx_phy_clk_pll_calc()
989 GENMASK(6, 0), in hdptx_phy_clk_pll_calc()
990 GENMASK(7, 0), in hdptx_phy_clk_pll_calc()
1007 cfg->sdm_en = k > 0 ? 1 : 0; in hdptx_phy_clk_pll_calc()
1023 u8 color_depth = (bit_rate & COLOR_DEPTH_MASK) ? 1 : 0; in hdptx_lcpll_cmn_config()
1029 for (; cfg->bit_rate != ~0; cfg++) in hdptx_lcpll_cmn_config()
1033 if (cfg->bit_rate == ~0) in hdptx_lcpll_cmn_config()
1047 hdptx_write(hdptx, CMN_REG0009, 0x0c); in hdptx_lcpll_cmn_config()
1048 hdptx_write(hdptx, CMN_REG000A, 0x83); in hdptx_lcpll_cmn_config()
1049 hdptx_write(hdptx, CMN_REG000B, 0x06); in hdptx_lcpll_cmn_config()
1050 hdptx_write(hdptx, CMN_REG000C, 0x20); in hdptx_lcpll_cmn_config()
1051 hdptx_write(hdptx, CMN_REG000D, 0xb8); in hdptx_lcpll_cmn_config()
1052 hdptx_write(hdptx, CMN_REG000E, 0x0f); in hdptx_lcpll_cmn_config()
1053 hdptx_write(hdptx, CMN_REG000F, 0x0f); in hdptx_lcpll_cmn_config()
1054 hdptx_write(hdptx, CMN_REG0010, 0x04); in hdptx_lcpll_cmn_config()
1055 hdptx_write(hdptx, CMN_REG0011, 0x00); in hdptx_lcpll_cmn_config()
1056 hdptx_write(hdptx, CMN_REG0012, 0x26); in hdptx_lcpll_cmn_config()
1057 hdptx_write(hdptx, CMN_REG0013, 0x22); in hdptx_lcpll_cmn_config()
1058 hdptx_write(hdptx, CMN_REG0014, 0x24); in hdptx_lcpll_cmn_config()
1059 hdptx_write(hdptx, CMN_REG0015, 0x77); in hdptx_lcpll_cmn_config()
1060 hdptx_write(hdptx, CMN_REG0016, 0x08); in hdptx_lcpll_cmn_config()
1061 hdptx_write(hdptx, CMN_REG0017, 0x00); in hdptx_lcpll_cmn_config()
1062 hdptx_write(hdptx, CMN_REG0018, 0x04); in hdptx_lcpll_cmn_config()
1063 hdptx_write(hdptx, CMN_REG0019, 0x48); in hdptx_lcpll_cmn_config()
1064 hdptx_write(hdptx, CMN_REG001A, 0x01); in hdptx_lcpll_cmn_config()
1065 hdptx_write(hdptx, CMN_REG001B, 0x00); in hdptx_lcpll_cmn_config()
1066 hdptx_write(hdptx, CMN_REG001C, 0x01); in hdptx_lcpll_cmn_config()
1067 hdptx_write(hdptx, CMN_REG001D, 0x64); in hdptx_lcpll_cmn_config()
1072 hdptx_write(hdptx, CMN_REG001F, 0x00); in hdptx_lcpll_cmn_config()
1077 hdptx_write(hdptx, CMN_REG0025, 0x10); in hdptx_lcpll_cmn_config()
1078 hdptx_write(hdptx, CMN_REG0026, 0x53); in hdptx_lcpll_cmn_config()
1079 hdptx_write(hdptx, CMN_REG0027, 0x01); in hdptx_lcpll_cmn_config()
1080 hdptx_write(hdptx, CMN_REG0028, 0x0d); in hdptx_lcpll_cmn_config()
1081 hdptx_write(hdptx, CMN_REG0029, 0x01); in hdptx_lcpll_cmn_config()
1087 hdptx_write(hdptx, CMN_REG002E, 0x02); in hdptx_lcpll_cmn_config()
1088 hdptx_write(hdptx, CMN_REG002F, 0x0d); in hdptx_lcpll_cmn_config()
1089 hdptx_write(hdptx, CMN_REG0030, 0x00); in hdptx_lcpll_cmn_config()
1090 hdptx_write(hdptx, CMN_REG0031, 0x20); in hdptx_lcpll_cmn_config()
1091 hdptx_write(hdptx, CMN_REG0032, 0x30); in hdptx_lcpll_cmn_config()
1092 hdptx_write(hdptx, CMN_REG0033, 0x0b); in hdptx_lcpll_cmn_config()
1093 hdptx_write(hdptx, CMN_REG0034, 0x23); in hdptx_lcpll_cmn_config()
1094 hdptx_write(hdptx, CMN_REG0035, 0x00); in hdptx_lcpll_cmn_config()
1095 hdptx_write(hdptx, CMN_REG0038, 0x00); in hdptx_lcpll_cmn_config()
1096 hdptx_write(hdptx, CMN_REG0039, 0x00); in hdptx_lcpll_cmn_config()
1097 hdptx_write(hdptx, CMN_REG003A, 0x00); in hdptx_lcpll_cmn_config()
1098 hdptx_write(hdptx, CMN_REG003B, 0x00); in hdptx_lcpll_cmn_config()
1099 hdptx_write(hdptx, CMN_REG003C, 0x80); in hdptx_lcpll_cmn_config()
1100 hdptx_write(hdptx, CMN_REG003D, 0x00); in hdptx_lcpll_cmn_config()
1101 hdptx_write(hdptx, CMN_REG003E, 0x0c); in hdptx_lcpll_cmn_config()
1102 hdptx_write(hdptx, CMN_REG003F, 0x83); in hdptx_lcpll_cmn_config()
1103 hdptx_write(hdptx, CMN_REG0040, 0x06); in hdptx_lcpll_cmn_config()
1104 hdptx_write(hdptx, CMN_REG0041, 0x20); in hdptx_lcpll_cmn_config()
1105 hdptx_write(hdptx, CMN_REG0042, 0xb8); in hdptx_lcpll_cmn_config()
1106 hdptx_write(hdptx, CMN_REG0043, 0x00); in hdptx_lcpll_cmn_config()
1107 hdptx_write(hdptx, CMN_REG0044, 0x46); in hdptx_lcpll_cmn_config()
1108 hdptx_write(hdptx, CMN_REG0045, 0x24); in hdptx_lcpll_cmn_config()
1109 hdptx_write(hdptx, CMN_REG0046, 0xff); in hdptx_lcpll_cmn_config()
1110 hdptx_write(hdptx, CMN_REG0047, 0x00); in hdptx_lcpll_cmn_config()
1111 hdptx_write(hdptx, CMN_REG0048, 0x44); in hdptx_lcpll_cmn_config()
1112 hdptx_write(hdptx, CMN_REG0049, 0xfa); in hdptx_lcpll_cmn_config()
1113 hdptx_write(hdptx, CMN_REG004A, 0x08); in hdptx_lcpll_cmn_config()
1114 hdptx_write(hdptx, CMN_REG004B, 0x00); in hdptx_lcpll_cmn_config()
1115 hdptx_write(hdptx, CMN_REG004C, 0x01); in hdptx_lcpll_cmn_config()
1116 hdptx_write(hdptx, CMN_REG004D, 0x64); in hdptx_lcpll_cmn_config()
1117 hdptx_write(hdptx, CMN_REG004E, 0x14); in hdptx_lcpll_cmn_config()
1118 hdptx_write(hdptx, CMN_REG004F, 0x00); in hdptx_lcpll_cmn_config()
1119 hdptx_write(hdptx, CMN_REG0050, 0x00); in hdptx_lcpll_cmn_config()
1120 hdptx_write(hdptx, CMN_REG0051, 0x00); in hdptx_lcpll_cmn_config()
1121 hdptx_write(hdptx, CMN_REG0055, 0x00); in hdptx_lcpll_cmn_config()
1122 hdptx_write(hdptx, CMN_REG0059, 0x11); in hdptx_lcpll_cmn_config()
1123 hdptx_write(hdptx, CMN_REG005A, 0x03); in hdptx_lcpll_cmn_config()
1124 hdptx_write(hdptx, CMN_REG005C, 0x05); in hdptx_lcpll_cmn_config()
1125 hdptx_write(hdptx, CMN_REG005D, 0x0c); in hdptx_lcpll_cmn_config()
1126 hdptx_write(hdptx, CMN_REG005E, 0x07); in hdptx_lcpll_cmn_config()
1127 hdptx_write(hdptx, CMN_REG005F, 0x01); in hdptx_lcpll_cmn_config()
1128 hdptx_write(hdptx, CMN_REG0060, 0x01); in hdptx_lcpll_cmn_config()
1129 hdptx_write(hdptx, CMN_REG0064, 0x07); in hdptx_lcpll_cmn_config()
1130 hdptx_write(hdptx, CMN_REG0065, 0x00); in hdptx_lcpll_cmn_config()
1131 hdptx_write(hdptx, CMN_REG0069, 0x00); in hdptx_lcpll_cmn_config()
1132 hdptx_write(hdptx, CMN_REG006B, 0x04); in hdptx_lcpll_cmn_config()
1133 hdptx_write(hdptx, CMN_REG006C, 0x00); in hdptx_lcpll_cmn_config()
1134 hdptx_write(hdptx, CMN_REG0070, 0x01); in hdptx_lcpll_cmn_config()
1135 hdptx_write(hdptx, CMN_REG0073, 0x30); in hdptx_lcpll_cmn_config()
1136 hdptx_write(hdptx, CMN_REG0074, 0x00); in hdptx_lcpll_cmn_config()
1137 hdptx_write(hdptx, CMN_REG0075, 0x20); in hdptx_lcpll_cmn_config()
1138 hdptx_write(hdptx, CMN_REG0076, 0x30); in hdptx_lcpll_cmn_config()
1139 hdptx_write(hdptx, CMN_REG0077, 0x08); in hdptx_lcpll_cmn_config()
1140 hdptx_write(hdptx, CMN_REG0078, 0x0c); in hdptx_lcpll_cmn_config()
1141 hdptx_write(hdptx, CMN_REG0079, 0x00); in hdptx_lcpll_cmn_config()
1142 hdptx_write(hdptx, CMN_REG007B, 0x00); in hdptx_lcpll_cmn_config()
1143 hdptx_write(hdptx, CMN_REG007C, 0x00); in hdptx_lcpll_cmn_config()
1144 hdptx_write(hdptx, CMN_REG007D, 0x00); in hdptx_lcpll_cmn_config()
1145 hdptx_write(hdptx, CMN_REG007E, 0x00); in hdptx_lcpll_cmn_config()
1146 hdptx_write(hdptx, CMN_REG007F, 0x00); in hdptx_lcpll_cmn_config()
1147 hdptx_write(hdptx, CMN_REG0080, 0x00); in hdptx_lcpll_cmn_config()
1148 hdptx_write(hdptx, CMN_REG0081, 0x09); in hdptx_lcpll_cmn_config()
1149 hdptx_write(hdptx, CMN_REG0082, 0x04); in hdptx_lcpll_cmn_config()
1150 hdptx_write(hdptx, CMN_REG0083, 0x24); in hdptx_lcpll_cmn_config()
1151 hdptx_write(hdptx, CMN_REG0084, 0x20); in hdptx_lcpll_cmn_config()
1152 hdptx_write(hdptx, CMN_REG0085, 0x03); in hdptx_lcpll_cmn_config()
1153 hdptx_write(hdptx, CMN_REG0086, 0x01); in hdptx_lcpll_cmn_config()
1158 hdptx_write(hdptx, CMN_REG0087, 0x0c); in hdptx_lcpll_cmn_config()
1159 hdptx_write(hdptx, CMN_REG0089, 0x02); in hdptx_lcpll_cmn_config()
1160 hdptx_write(hdptx, CMN_REG008A, 0x55); in hdptx_lcpll_cmn_config()
1161 hdptx_write(hdptx, CMN_REG008B, 0x25); in hdptx_lcpll_cmn_config()
1162 hdptx_write(hdptx, CMN_REG008C, 0x2c); in hdptx_lcpll_cmn_config()
1163 hdptx_write(hdptx, CMN_REG008D, 0x22); in hdptx_lcpll_cmn_config()
1164 hdptx_write(hdptx, CMN_REG008E, 0x14); in hdptx_lcpll_cmn_config()
1165 hdptx_write(hdptx, CMN_REG008F, 0x20); in hdptx_lcpll_cmn_config()
1166 hdptx_write(hdptx, CMN_REG0090, 0x00); in hdptx_lcpll_cmn_config()
1167 hdptx_write(hdptx, CMN_REG0091, 0x00); in hdptx_lcpll_cmn_config()
1168 hdptx_write(hdptx, CMN_REG0092, 0x00); in hdptx_lcpll_cmn_config()
1169 hdptx_write(hdptx, CMN_REG0093, 0x00); in hdptx_lcpll_cmn_config()
1170 hdptx_write(hdptx, CMN_REG0095, 0x00); in hdptx_lcpll_cmn_config()
1171 hdptx_write(hdptx, CMN_REG0097, 0x00); in hdptx_lcpll_cmn_config()
1172 hdptx_write(hdptx, CMN_REG0099, 0x00); in hdptx_lcpll_cmn_config()
1173 hdptx_write(hdptx, CMN_REG009A, 0x11); in hdptx_lcpll_cmn_config()
1174 hdptx_write(hdptx, CMN_REG009B, 0x10); in hdptx_lcpll_cmn_config()
1175 hdptx_write(hdptx, SB_REG0114, 0x00); in hdptx_lcpll_cmn_config()
1176 hdptx_write(hdptx, SB_REG0115, 0x00); in hdptx_lcpll_cmn_config()
1177 hdptx_write(hdptx, SB_REG0116, 0x00); in hdptx_lcpll_cmn_config()
1178 hdptx_write(hdptx, SB_REG0117, 0x00); in hdptx_lcpll_cmn_config()
1186 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; in hdptx_ropll_cmn_config()
1188 struct ropll_config rc = {0}; in hdptx_ropll_cmn_config()
1193 for (; cfg->bit_rate != ~0; cfg++) in hdptx_ropll_cmn_config()
1197 if (cfg->bit_rate == ~0) { in hdptx_ropll_cmn_config()
1221 hdptx_write(hdptx, CMN_REG0008, 0x00); in hdptx_ropll_cmn_config()
1222 hdptx_write(hdptx, CMN_REG0009, 0x0c); in hdptx_ropll_cmn_config()
1223 hdptx_write(hdptx, CMN_REG000A, 0x83); in hdptx_ropll_cmn_config()
1224 hdptx_write(hdptx, CMN_REG000B, 0x06); in hdptx_ropll_cmn_config()
1225 hdptx_write(hdptx, CMN_REG000C, 0x20); in hdptx_ropll_cmn_config()
1226 hdptx_write(hdptx, CMN_REG000D, 0xb8); in hdptx_ropll_cmn_config()
1227 hdptx_write(hdptx, CMN_REG000E, 0x0f); in hdptx_ropll_cmn_config()
1228 hdptx_write(hdptx, CMN_REG000F, 0x0f); in hdptx_ropll_cmn_config()
1229 hdptx_write(hdptx, CMN_REG0010, 0x04); in hdptx_ropll_cmn_config()
1230 hdptx_write(hdptx, CMN_REG0011, 0x01); in hdptx_ropll_cmn_config()
1231 hdptx_write(hdptx, CMN_REG0012, 0x26); in hdptx_ropll_cmn_config()
1232 hdptx_write(hdptx, CMN_REG0013, 0x22); in hdptx_ropll_cmn_config()
1233 hdptx_write(hdptx, CMN_REG0014, 0x24); in hdptx_ropll_cmn_config()
1234 hdptx_write(hdptx, CMN_REG0015, 0x77); in hdptx_ropll_cmn_config()
1235 hdptx_write(hdptx, CMN_REG0016, 0x08); in hdptx_ropll_cmn_config()
1236 hdptx_write(hdptx, CMN_REG0017, 0x20); in hdptx_ropll_cmn_config()
1237 hdptx_write(hdptx, CMN_REG0018, 0x04); in hdptx_ropll_cmn_config()
1238 hdptx_write(hdptx, CMN_REG0019, 0x48); in hdptx_ropll_cmn_config()
1239 hdptx_write(hdptx, CMN_REG001A, 0x01); in hdptx_ropll_cmn_config()
1240 hdptx_write(hdptx, CMN_REG001B, 0x00); in hdptx_ropll_cmn_config()
1241 hdptx_write(hdptx, CMN_REG001C, 0x01); in hdptx_ropll_cmn_config()
1242 hdptx_write(hdptx, CMN_REG001D, 0x64); in hdptx_ropll_cmn_config()
1243 hdptx_write(hdptx, CMN_REG001E, 0x14); in hdptx_ropll_cmn_config()
1244 hdptx_write(hdptx, CMN_REG001F, 0x00); in hdptx_ropll_cmn_config()
1245 hdptx_write(hdptx, CMN_REG0020, 0x00); in hdptx_ropll_cmn_config()
1246 hdptx_write(hdptx, CMN_REG0021, 0x00); in hdptx_ropll_cmn_config()
1247 hdptx_write(hdptx, CMN_REG0022, 0x11); in hdptx_ropll_cmn_config()
1248 hdptx_write(hdptx, CMN_REG0023, 0x00); in hdptx_ropll_cmn_config()
1249 hdptx_write(hdptx, CMN_REG0024, 0x00); in hdptx_ropll_cmn_config()
1250 hdptx_write(hdptx, CMN_REG0025, 0x53); in hdptx_ropll_cmn_config()
1251 hdptx_write(hdptx, CMN_REG0026, 0x00); in hdptx_ropll_cmn_config()
1252 hdptx_write(hdptx, CMN_REG0027, 0x00); in hdptx_ropll_cmn_config()
1253 hdptx_write(hdptx, CMN_REG0028, 0x01); in hdptx_ropll_cmn_config()
1254 hdptx_write(hdptx, CMN_REG0029, 0x01); in hdptx_ropll_cmn_config()
1255 hdptx_write(hdptx, CMN_REG002A, 0x00); in hdptx_ropll_cmn_config()
1256 hdptx_write(hdptx, CMN_REG002B, 0x00); in hdptx_ropll_cmn_config()
1257 hdptx_write(hdptx, CMN_REG002C, 0x00); in hdptx_ropll_cmn_config()
1258 hdptx_write(hdptx, CMN_REG002D, 0x00); in hdptx_ropll_cmn_config()
1259 hdptx_write(hdptx, CMN_REG002E, 0x04); in hdptx_ropll_cmn_config()
1260 hdptx_write(hdptx, CMN_REG002F, 0x00); in hdptx_ropll_cmn_config()
1261 hdptx_write(hdptx, CMN_REG0030, 0x20); in hdptx_ropll_cmn_config()
1262 hdptx_write(hdptx, CMN_REG0031, 0x30); in hdptx_ropll_cmn_config()
1263 hdptx_write(hdptx, CMN_REG0032, 0x0b); in hdptx_ropll_cmn_config()
1264 hdptx_write(hdptx, CMN_REG0033, 0x23); in hdptx_ropll_cmn_config()
1265 hdptx_write(hdptx, CMN_REG0034, 0x00); in hdptx_ropll_cmn_config()
1266 hdptx_write(hdptx, CMN_REG0035, 0x00); in hdptx_ropll_cmn_config()
1267 hdptx_write(hdptx, CMN_REG0038, 0x00); in hdptx_ropll_cmn_config()
1268 hdptx_write(hdptx, CMN_REG0039, 0x00); in hdptx_ropll_cmn_config()
1269 hdptx_write(hdptx, CMN_REG003A, 0x00); in hdptx_ropll_cmn_config()
1270 hdptx_write(hdptx, CMN_REG003B, 0x00); in hdptx_ropll_cmn_config()
1271 hdptx_write(hdptx, CMN_REG003C, 0x80); in hdptx_ropll_cmn_config()
1272 hdptx_write(hdptx, CMN_REG003D, 0x40); in hdptx_ropll_cmn_config()
1273 hdptx_write(hdptx, CMN_REG003E, 0x0c); in hdptx_ropll_cmn_config()
1274 hdptx_write(hdptx, CMN_REG003F, 0x83); in hdptx_ropll_cmn_config()
1275 hdptx_write(hdptx, CMN_REG0040, 0x06); in hdptx_ropll_cmn_config()
1276 hdptx_write(hdptx, CMN_REG0041, 0x20); in hdptx_ropll_cmn_config()
1277 hdptx_write(hdptx, CMN_REG0042, 0x78); in hdptx_ropll_cmn_config()
1278 hdptx_write(hdptx, CMN_REG0043, 0x00); in hdptx_ropll_cmn_config()
1279 hdptx_write(hdptx, CMN_REG0044, 0x46); in hdptx_ropll_cmn_config()
1280 hdptx_write(hdptx, CMN_REG0045, 0x24); in hdptx_ropll_cmn_config()
1281 hdptx_write(hdptx, CMN_REG0046, 0xdd); in hdptx_ropll_cmn_config()
1282 hdptx_write(hdptx, CMN_REG0047, 0x00); in hdptx_ropll_cmn_config()
1283 hdptx_write(hdptx, CMN_REG0048, 0x11); in hdptx_ropll_cmn_config()
1284 hdptx_write(hdptx, CMN_REG0049, 0xfa); in hdptx_ropll_cmn_config()
1285 hdptx_write(hdptx, CMN_REG004A, 0x08); in hdptx_ropll_cmn_config()
1286 hdptx_write(hdptx, CMN_REG004B, 0x00); in hdptx_ropll_cmn_config()
1287 hdptx_write(hdptx, CMN_REG004C, 0x01); in hdptx_ropll_cmn_config()
1288 hdptx_write(hdptx, CMN_REG004D, 0x64); in hdptx_ropll_cmn_config()
1289 hdptx_write(hdptx, CMN_REG004E, 0x34); in hdptx_ropll_cmn_config()
1290 hdptx_write(hdptx, CMN_REG004F, 0x00); in hdptx_ropll_cmn_config()
1291 hdptx_write(hdptx, CMN_REG0050, 0x00); in hdptx_ropll_cmn_config()
1300 hdptx_write(hdptx, CMN_REG005C, 0x25); in hdptx_ropll_cmn_config()
1301 hdptx_write(hdptx, CMN_REG005D, 0x0c); in hdptx_ropll_cmn_config()
1302 hdptx_write(hdptx, CMN_REG005E, 0x4f); in hdptx_ropll_cmn_config()
1306 hdptx_update_bits(hdptx, CMN_REG005E, 0xf, 0); in hdptx_ropll_cmn_config()
1308 hdptx_write(hdptx, CMN_REG005F, 0x01); in hdptx_ropll_cmn_config()
1321 hdptx_write(hdptx, CMN_REG006B, 0x04); in hdptx_ropll_cmn_config()
1323 hdptx_write(hdptx, CMN_REG0073, 0x30); in hdptx_ropll_cmn_config()
1324 hdptx_write(hdptx, CMN_REG0074, 0x04); in hdptx_ropll_cmn_config()
1325 hdptx_write(hdptx, CMN_REG0075, 0x20); in hdptx_ropll_cmn_config()
1326 hdptx_write(hdptx, CMN_REG0076, 0x30); in hdptx_ropll_cmn_config()
1327 hdptx_write(hdptx, CMN_REG0077, 0x08); in hdptx_ropll_cmn_config()
1328 hdptx_write(hdptx, CMN_REG0078, 0x0c); in hdptx_ropll_cmn_config()
1329 hdptx_write(hdptx, CMN_REG0079, 0x00); in hdptx_ropll_cmn_config()
1330 hdptx_write(hdptx, CMN_REG007B, 0x00); in hdptx_ropll_cmn_config()
1331 hdptx_write(hdptx, CMN_REG007C, 0x00); in hdptx_ropll_cmn_config()
1332 hdptx_write(hdptx, CMN_REG007D, 0x00); in hdptx_ropll_cmn_config()
1333 hdptx_write(hdptx, CMN_REG007E, 0x00); in hdptx_ropll_cmn_config()
1334 hdptx_write(hdptx, CMN_REG007F, 0x00); in hdptx_ropll_cmn_config()
1335 hdptx_write(hdptx, CMN_REG0080, 0x00); in hdptx_ropll_cmn_config()
1336 hdptx_write(hdptx, CMN_REG0081, 0x01); in hdptx_ropll_cmn_config()
1337 hdptx_write(hdptx, CMN_REG0082, 0x04); in hdptx_ropll_cmn_config()
1338 hdptx_write(hdptx, CMN_REG0083, 0x24); in hdptx_ropll_cmn_config()
1339 hdptx_write(hdptx, CMN_REG0084, 0x20); in hdptx_ropll_cmn_config()
1340 hdptx_write(hdptx, CMN_REG0085, 0x03); in hdptx_ropll_cmn_config()
1350 hdptx_write(hdptx, CMN_REG0087, 0x04); in hdptx_ropll_cmn_config()
1351 hdptx_write(hdptx, CMN_REG0089, 0x00); in hdptx_ropll_cmn_config()
1352 hdptx_write(hdptx, CMN_REG008A, 0x55); in hdptx_ropll_cmn_config()
1353 hdptx_write(hdptx, CMN_REG008B, 0x25); in hdptx_ropll_cmn_config()
1354 hdptx_write(hdptx, CMN_REG008C, 0x2c); in hdptx_ropll_cmn_config()
1355 hdptx_write(hdptx, CMN_REG008D, 0x22); in hdptx_ropll_cmn_config()
1356 hdptx_write(hdptx, CMN_REG008E, 0x14); in hdptx_ropll_cmn_config()
1357 hdptx_write(hdptx, CMN_REG008F, 0x20); in hdptx_ropll_cmn_config()
1358 hdptx_write(hdptx, CMN_REG0090, 0x00); in hdptx_ropll_cmn_config()
1359 hdptx_write(hdptx, CMN_REG0091, 0x00); in hdptx_ropll_cmn_config()
1360 hdptx_write(hdptx, CMN_REG0092, 0x00); in hdptx_ropll_cmn_config()
1361 hdptx_write(hdptx, CMN_REG0093, 0x00); in hdptx_ropll_cmn_config()
1362 hdptx_write(hdptx, CMN_REG0095, 0x00); in hdptx_ropll_cmn_config()
1363 hdptx_write(hdptx, CMN_REG0097, 0x02); in hdptx_ropll_cmn_config()
1364 hdptx_write(hdptx, CMN_REG0099, 0x04); in hdptx_ropll_cmn_config()
1365 hdptx_write(hdptx, CMN_REG009A, 0x11); in hdptx_ropll_cmn_config()
1366 hdptx_write(hdptx, CMN_REG009B, 0x00); in hdptx_ropll_cmn_config()
1374 u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0; in hdptx_ropll_tmds_mode_config()
1379 hdptx_write(hdptx, SB_REG0114, 0x00); in hdptx_ropll_tmds_mode_config()
1380 hdptx_write(hdptx, SB_REG0115, 0x00); in hdptx_ropll_tmds_mode_config()
1381 hdptx_write(hdptx, SB_REG0116, 0x00); in hdptx_ropll_tmds_mode_config()
1382 hdptx_write(hdptx, SB_REG0117, 0x00); in hdptx_ropll_tmds_mode_config()
1383 hdptx_write(hdptx, LNTOP_REG0200, 0x06); in hdptx_ropll_tmds_mode_config()
1387 hdptx_write(hdptx, LNTOP_REG0201, 0x00); in hdptx_ropll_tmds_mode_config()
1388 hdptx_write(hdptx, LNTOP_REG0202, 0x00); in hdptx_ropll_tmds_mode_config()
1389 hdptx_write(hdptx, LNTOP_REG0203, 0x0f); in hdptx_ropll_tmds_mode_config()
1390 hdptx_write(hdptx, LNTOP_REG0204, 0xff); in hdptx_ropll_tmds_mode_config()
1391 hdptx_write(hdptx, LNTOP_REG0205, 0xff); in hdptx_ropll_tmds_mode_config()
1394 hdptx_write(hdptx, LNTOP_REG0201, 0x07); in hdptx_ropll_tmds_mode_config()
1395 hdptx_write(hdptx, LNTOP_REG0202, 0xc1); in hdptx_ropll_tmds_mode_config()
1396 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); in hdptx_ropll_tmds_mode_config()
1397 hdptx_write(hdptx, LNTOP_REG0204, 0x7c); in hdptx_ropll_tmds_mode_config()
1398 hdptx_write(hdptx, LNTOP_REG0205, 0x1f); in hdptx_ropll_tmds_mode_config()
1401 hdptx_write(hdptx, LNTOP_REG0206, 0x07); in hdptx_ropll_tmds_mode_config()
1402 hdptx_write(hdptx, LANE_REG0303, 0x0c); in hdptx_ropll_tmds_mode_config()
1403 hdptx_write(hdptx, LANE_REG0307, 0x20); in hdptx_ropll_tmds_mode_config()
1404 hdptx_write(hdptx, LANE_REG030A, 0x17); in hdptx_ropll_tmds_mode_config()
1405 hdptx_write(hdptx, LANE_REG030B, 0x77); in hdptx_ropll_tmds_mode_config()
1406 hdptx_write(hdptx, LANE_REG030C, 0x77); in hdptx_ropll_tmds_mode_config()
1407 hdptx_write(hdptx, LANE_REG030D, 0x77); in hdptx_ropll_tmds_mode_config()
1408 hdptx_write(hdptx, LANE_REG030E, 0x38); in hdptx_ropll_tmds_mode_config()
1409 hdptx_write(hdptx, LANE_REG0310, 0x03); in hdptx_ropll_tmds_mode_config()
1410 hdptx_write(hdptx, LANE_REG0311, 0x0f); in hdptx_ropll_tmds_mode_config()
1411 hdptx_write(hdptx, LANE_REG0312, 0x00); in hdptx_ropll_tmds_mode_config()
1412 hdptx_write(hdptx, LANE_REG0316, 0x02); in hdptx_ropll_tmds_mode_config()
1413 hdptx_write(hdptx, LANE_REG031B, 0x01); in hdptx_ropll_tmds_mode_config()
1414 hdptx_write(hdptx, LANE_REG031E, 0x00); in hdptx_ropll_tmds_mode_config()
1415 hdptx_write(hdptx, LANE_REG031F, 0x15); in hdptx_ropll_tmds_mode_config()
1416 hdptx_write(hdptx, LANE_REG0320, 0xa0); in hdptx_ropll_tmds_mode_config()
1417 hdptx_write(hdptx, LANE_REG0403, 0x0c); in hdptx_ropll_tmds_mode_config()
1418 hdptx_write(hdptx, LANE_REG0407, 0x20); in hdptx_ropll_tmds_mode_config()
1419 hdptx_write(hdptx, LANE_REG040A, 0x17); in hdptx_ropll_tmds_mode_config()
1420 hdptx_write(hdptx, LANE_REG040B, 0x77); in hdptx_ropll_tmds_mode_config()
1421 hdptx_write(hdptx, LANE_REG040C, 0x77); in hdptx_ropll_tmds_mode_config()
1422 hdptx_write(hdptx, LANE_REG040D, 0x77); in hdptx_ropll_tmds_mode_config()
1423 hdptx_write(hdptx, LANE_REG040E, 0x38); in hdptx_ropll_tmds_mode_config()
1424 hdptx_write(hdptx, LANE_REG0410, 0x03); in hdptx_ropll_tmds_mode_config()
1425 hdptx_write(hdptx, LANE_REG0411, 0x0f); in hdptx_ropll_tmds_mode_config()
1426 hdptx_write(hdptx, LANE_REG0412, 0x00); in hdptx_ropll_tmds_mode_config()
1427 hdptx_write(hdptx, LANE_REG0416, 0x02); in hdptx_ropll_tmds_mode_config()
1428 hdptx_write(hdptx, LANE_REG041B, 0x01); in hdptx_ropll_tmds_mode_config()
1429 hdptx_write(hdptx, LANE_REG041E, 0x00); in hdptx_ropll_tmds_mode_config()
1430 hdptx_write(hdptx, LANE_REG041F, 0x15); in hdptx_ropll_tmds_mode_config()
1431 hdptx_write(hdptx, LANE_REG0420, 0xa0); in hdptx_ropll_tmds_mode_config()
1432 hdptx_write(hdptx, LANE_REG0503, 0x0c); in hdptx_ropll_tmds_mode_config()
1433 hdptx_write(hdptx, LANE_REG0507, 0x20); in hdptx_ropll_tmds_mode_config()
1434 hdptx_write(hdptx, LANE_REG050A, 0x17); in hdptx_ropll_tmds_mode_config()
1435 hdptx_write(hdptx, LANE_REG050B, 0x77); in hdptx_ropll_tmds_mode_config()
1436 hdptx_write(hdptx, LANE_REG050C, 0x77); in hdptx_ropll_tmds_mode_config()
1437 hdptx_write(hdptx, LANE_REG050D, 0x77); in hdptx_ropll_tmds_mode_config()
1438 hdptx_write(hdptx, LANE_REG050E, 0x38); in hdptx_ropll_tmds_mode_config()
1439 hdptx_write(hdptx, LANE_REG0510, 0x03); in hdptx_ropll_tmds_mode_config()
1440 hdptx_write(hdptx, LANE_REG0511, 0x0f); in hdptx_ropll_tmds_mode_config()
1441 hdptx_write(hdptx, LANE_REG0512, 0x00); in hdptx_ropll_tmds_mode_config()
1442 hdptx_write(hdptx, LANE_REG0516, 0x02); in hdptx_ropll_tmds_mode_config()
1443 hdptx_write(hdptx, LANE_REG051B, 0x01); in hdptx_ropll_tmds_mode_config()
1444 hdptx_write(hdptx, LANE_REG051E, 0x00); in hdptx_ropll_tmds_mode_config()
1445 hdptx_write(hdptx, LANE_REG051F, 0x15); in hdptx_ropll_tmds_mode_config()
1446 hdptx_write(hdptx, LANE_REG0520, 0xa0); in hdptx_ropll_tmds_mode_config()
1447 hdptx_write(hdptx, LANE_REG0603, 0x0c); in hdptx_ropll_tmds_mode_config()
1448 hdptx_write(hdptx, LANE_REG0607, 0x20); in hdptx_ropll_tmds_mode_config()
1449 hdptx_write(hdptx, LANE_REG060A, 0x17); in hdptx_ropll_tmds_mode_config()
1450 hdptx_write(hdptx, LANE_REG060B, 0x77); in hdptx_ropll_tmds_mode_config()
1451 hdptx_write(hdptx, LANE_REG060C, 0x77); in hdptx_ropll_tmds_mode_config()
1452 hdptx_write(hdptx, LANE_REG060D, 0x77); in hdptx_ropll_tmds_mode_config()
1453 hdptx_write(hdptx, LANE_REG060E, 0x38); in hdptx_ropll_tmds_mode_config()
1454 hdptx_write(hdptx, LANE_REG0610, 0x03); in hdptx_ropll_tmds_mode_config()
1455 hdptx_write(hdptx, LANE_REG0611, 0x0f); in hdptx_ropll_tmds_mode_config()
1456 hdptx_write(hdptx, LANE_REG0612, 0x00); in hdptx_ropll_tmds_mode_config()
1457 hdptx_write(hdptx, LANE_REG0616, 0x02); in hdptx_ropll_tmds_mode_config()
1458 hdptx_write(hdptx, LANE_REG061B, 0x01); in hdptx_ropll_tmds_mode_config()
1459 hdptx_write(hdptx, LANE_REG061E, 0x08); in hdptx_ropll_tmds_mode_config()
1462 hdptx_write(hdptx, LANE_REG031E, 0x02); in hdptx_ropll_tmds_mode_config()
1463 hdptx_write(hdptx, LANE_REG041E, 0x02); in hdptx_ropll_tmds_mode_config()
1464 hdptx_write(hdptx, LANE_REG051E, 0x02); in hdptx_ropll_tmds_mode_config()
1465 hdptx_write(hdptx, LANE_REG061E, 0x0a); in hdptx_ropll_tmds_mode_config()
1467 hdptx_write(hdptx, LANE_REG061F, 0x15); in hdptx_ropll_tmds_mode_config()
1468 hdptx_write(hdptx, LANE_REG0620, 0xa0); in hdptx_ropll_tmds_mode_config()
1470 hdptx_write(hdptx, LANE_REG0303, 0x2f); in hdptx_ropll_tmds_mode_config()
1471 hdptx_write(hdptx, LANE_REG0403, 0x2f); in hdptx_ropll_tmds_mode_config()
1472 hdptx_write(hdptx, LANE_REG0503, 0x2f); in hdptx_ropll_tmds_mode_config()
1473 hdptx_write(hdptx, LANE_REG0603, 0x2f); in hdptx_ropll_tmds_mode_config()
1474 hdptx_write(hdptx, LANE_REG0305, 0x03); in hdptx_ropll_tmds_mode_config()
1475 hdptx_write(hdptx, LANE_REG0405, 0x03); in hdptx_ropll_tmds_mode_config()
1476 hdptx_write(hdptx, LANE_REG0505, 0x03); in hdptx_ropll_tmds_mode_config()
1477 hdptx_write(hdptx, LANE_REG0605, 0x03); in hdptx_ropll_tmds_mode_config()
1478 hdptx_write(hdptx, LANE_REG0306, 0x1c); in hdptx_ropll_tmds_mode_config()
1479 hdptx_write(hdptx, LANE_REG0406, 0x1c); in hdptx_ropll_tmds_mode_config()
1480 hdptx_write(hdptx, LANE_REG0506, 0x1c); in hdptx_ropll_tmds_mode_config()
1481 hdptx_write(hdptx, LANE_REG0606, 0x1c); in hdptx_ropll_tmds_mode_config()
1510 hdptx_write(hdptx, CMN_REG0008, 0xd0); in hdptx_lcpll_ropll_cmn_config()
1511 hdptx_write(hdptx, CMN_REG0009, 0x0c); in hdptx_lcpll_ropll_cmn_config()
1512 hdptx_write(hdptx, CMN_REG000A, 0x83); in hdptx_lcpll_ropll_cmn_config()
1513 hdptx_write(hdptx, CMN_REG000B, 0x06); in hdptx_lcpll_ropll_cmn_config()
1514 hdptx_write(hdptx, CMN_REG000C, 0x20); in hdptx_lcpll_ropll_cmn_config()
1515 hdptx_write(hdptx, CMN_REG000D, 0xb8); in hdptx_lcpll_ropll_cmn_config()
1516 hdptx_write(hdptx, CMN_REG000E, 0x0f); in hdptx_lcpll_ropll_cmn_config()
1517 hdptx_write(hdptx, CMN_REG000F, 0x0f); in hdptx_lcpll_ropll_cmn_config()
1518 hdptx_write(hdptx, CMN_REG0010, 0x04); in hdptx_lcpll_ropll_cmn_config()
1519 hdptx_write(hdptx, CMN_REG0011, 0x00); in hdptx_lcpll_ropll_cmn_config()
1520 hdptx_write(hdptx, CMN_REG0012, 0x26); in hdptx_lcpll_ropll_cmn_config()
1521 hdptx_write(hdptx, CMN_REG0013, 0x22); in hdptx_lcpll_ropll_cmn_config()
1522 hdptx_write(hdptx, CMN_REG0014, 0x24); in hdptx_lcpll_ropll_cmn_config()
1523 hdptx_write(hdptx, CMN_REG0015, 0x77); in hdptx_lcpll_ropll_cmn_config()
1524 hdptx_write(hdptx, CMN_REG0016, 0x08); in hdptx_lcpll_ropll_cmn_config()
1525 hdptx_write(hdptx, CMN_REG0017, 0x00); in hdptx_lcpll_ropll_cmn_config()
1526 hdptx_write(hdptx, CMN_REG0018, 0x04); in hdptx_lcpll_ropll_cmn_config()
1527 hdptx_write(hdptx, CMN_REG0019, 0x48); in hdptx_lcpll_ropll_cmn_config()
1528 hdptx_write(hdptx, CMN_REG001A, 0x01); in hdptx_lcpll_ropll_cmn_config()
1529 hdptx_write(hdptx, CMN_REG001B, 0x00); in hdptx_lcpll_ropll_cmn_config()
1530 hdptx_write(hdptx, CMN_REG001C, 0x01); in hdptx_lcpll_ropll_cmn_config()
1531 hdptx_write(hdptx, CMN_REG001D, 0x64); in hdptx_lcpll_ropll_cmn_config()
1532 hdptx_write(hdptx, CMN_REG001E, 0x35); in hdptx_lcpll_ropll_cmn_config()
1533 hdptx_write(hdptx, CMN_REG001F, 0x00); in hdptx_lcpll_ropll_cmn_config()
1534 hdptx_write(hdptx, CMN_REG0020, 0x6b); in hdptx_lcpll_ropll_cmn_config()
1535 hdptx_write(hdptx, CMN_REG0021, 0x6b); in hdptx_lcpll_ropll_cmn_config()
1536 hdptx_write(hdptx, CMN_REG0022, 0x11); in hdptx_lcpll_ropll_cmn_config()
1537 hdptx_write(hdptx, CMN_REG0024, 0x00); in hdptx_lcpll_ropll_cmn_config()
1538 hdptx_write(hdptx, CMN_REG0025, 0x10); in hdptx_lcpll_ropll_cmn_config()
1539 hdptx_write(hdptx, CMN_REG0026, 0x53); in hdptx_lcpll_ropll_cmn_config()
1540 hdptx_write(hdptx, CMN_REG0027, 0x15); in hdptx_lcpll_ropll_cmn_config()
1541 hdptx_write(hdptx, CMN_REG0028, 0x0d); in hdptx_lcpll_ropll_cmn_config()
1542 hdptx_write(hdptx, CMN_REG0029, 0x01); in hdptx_lcpll_ropll_cmn_config()
1543 hdptx_write(hdptx, CMN_REG002A, 0x09); in hdptx_lcpll_ropll_cmn_config()
1544 hdptx_write(hdptx, CMN_REG002B, 0x01); in hdptx_lcpll_ropll_cmn_config()
1545 hdptx_write(hdptx, CMN_REG002C, 0x02); in hdptx_lcpll_ropll_cmn_config()
1546 hdptx_write(hdptx, CMN_REG002D, 0x02); in hdptx_lcpll_ropll_cmn_config()
1547 hdptx_write(hdptx, CMN_REG002E, 0x0d); in hdptx_lcpll_ropll_cmn_config()
1548 hdptx_write(hdptx, CMN_REG002F, 0x61); in hdptx_lcpll_ropll_cmn_config()
1549 hdptx_write(hdptx, CMN_REG0030, 0x00); in hdptx_lcpll_ropll_cmn_config()
1550 hdptx_write(hdptx, CMN_REG0031, 0x20); in hdptx_lcpll_ropll_cmn_config()
1551 hdptx_write(hdptx, CMN_REG0032, 0x30); in hdptx_lcpll_ropll_cmn_config()
1552 hdptx_write(hdptx, CMN_REG0033, 0x0b); in hdptx_lcpll_ropll_cmn_config()
1553 hdptx_write(hdptx, CMN_REG0034, 0x23); in hdptx_lcpll_ropll_cmn_config()
1554 hdptx_write(hdptx, CMN_REG0035, 0x00); in hdptx_lcpll_ropll_cmn_config()
1555 hdptx_write(hdptx, CMN_REG0037, 0x00); in hdptx_lcpll_ropll_cmn_config()
1556 hdptx_write(hdptx, CMN_REG0038, 0x00); in hdptx_lcpll_ropll_cmn_config()
1557 hdptx_write(hdptx, CMN_REG0039, 0x00); in hdptx_lcpll_ropll_cmn_config()
1558 hdptx_write(hdptx, CMN_REG003A, 0x00); in hdptx_lcpll_ropll_cmn_config()
1559 hdptx_write(hdptx, CMN_REG003B, 0x00); in hdptx_lcpll_ropll_cmn_config()
1560 hdptx_write(hdptx, CMN_REG003C, 0x80); in hdptx_lcpll_ropll_cmn_config()
1561 hdptx_write(hdptx, CMN_REG003D, 0xc0); in hdptx_lcpll_ropll_cmn_config()
1562 hdptx_write(hdptx, CMN_REG003E, 0x0c); in hdptx_lcpll_ropll_cmn_config()
1563 hdptx_write(hdptx, CMN_REG003F, 0x83); in hdptx_lcpll_ropll_cmn_config()
1564 hdptx_write(hdptx, CMN_REG0040, 0x06); in hdptx_lcpll_ropll_cmn_config()
1565 hdptx_write(hdptx, CMN_REG0041, 0x20); in hdptx_lcpll_ropll_cmn_config()
1566 hdptx_write(hdptx, CMN_REG0042, 0xb8); in hdptx_lcpll_ropll_cmn_config()
1567 hdptx_write(hdptx, CMN_REG0043, 0x00); in hdptx_lcpll_ropll_cmn_config()
1568 hdptx_write(hdptx, CMN_REG0044, 0x46); in hdptx_lcpll_ropll_cmn_config()
1569 hdptx_write(hdptx, CMN_REG0045, 0x24); in hdptx_lcpll_ropll_cmn_config()
1570 hdptx_write(hdptx, CMN_REG0046, 0xff); in hdptx_lcpll_ropll_cmn_config()
1571 hdptx_write(hdptx, CMN_REG0047, 0x00); in hdptx_lcpll_ropll_cmn_config()
1572 hdptx_write(hdptx, CMN_REG0048, 0x44); in hdptx_lcpll_ropll_cmn_config()
1573 hdptx_write(hdptx, CMN_REG0049, 0xfa); in hdptx_lcpll_ropll_cmn_config()
1574 hdptx_write(hdptx, CMN_REG004A, 0x08); in hdptx_lcpll_ropll_cmn_config()
1575 hdptx_write(hdptx, CMN_REG004B, 0x00); in hdptx_lcpll_ropll_cmn_config()
1576 hdptx_write(hdptx, CMN_REG004C, 0x01); in hdptx_lcpll_ropll_cmn_config()
1577 hdptx_write(hdptx, CMN_REG004D, 0x64); in hdptx_lcpll_ropll_cmn_config()
1578 hdptx_write(hdptx, CMN_REG004E, 0x14); in hdptx_lcpll_ropll_cmn_config()
1579 hdptx_write(hdptx, CMN_REG004F, 0x00); in hdptx_lcpll_ropll_cmn_config()
1580 hdptx_write(hdptx, CMN_REG0050, 0x00); in hdptx_lcpll_ropll_cmn_config()
1581 hdptx_write(hdptx, CMN_REG0054, 0x19); in hdptx_lcpll_ropll_cmn_config()
1582 hdptx_write(hdptx, CMN_REG0058, 0x19); in hdptx_lcpll_ropll_cmn_config()
1583 hdptx_write(hdptx, CMN_REG0059, 0x11); in hdptx_lcpll_ropll_cmn_config()
1584 hdptx_write(hdptx, CMN_REG005B, 0x30); in hdptx_lcpll_ropll_cmn_config()
1585 hdptx_write(hdptx, CMN_REG005C, 0x25); in hdptx_lcpll_ropll_cmn_config()
1586 hdptx_write(hdptx, CMN_REG005D, 0x14); in hdptx_lcpll_ropll_cmn_config()
1587 hdptx_write(hdptx, CMN_REG005E, 0x0e); in hdptx_lcpll_ropll_cmn_config()
1588 hdptx_write(hdptx, CMN_REG005F, 0x01); in hdptx_lcpll_ropll_cmn_config()
1589 hdptx_write(hdptx, CMN_REG0063, 0x01); in hdptx_lcpll_ropll_cmn_config()
1590 hdptx_write(hdptx, CMN_REG0064, 0x0e); in hdptx_lcpll_ropll_cmn_config()
1591 hdptx_write(hdptx, CMN_REG0068, 0x00); in hdptx_lcpll_ropll_cmn_config()
1592 hdptx_write(hdptx, CMN_REG0069, 0x02); in hdptx_lcpll_ropll_cmn_config()
1593 hdptx_write(hdptx, CMN_REG006B, 0x00); in hdptx_lcpll_ropll_cmn_config()
1594 hdptx_write(hdptx, CMN_REG006F, 0x00); in hdptx_lcpll_ropll_cmn_config()
1595 hdptx_write(hdptx, CMN_REG0073, 0x02); in hdptx_lcpll_ropll_cmn_config()
1596 hdptx_write(hdptx, CMN_REG0074, 0x00); in hdptx_lcpll_ropll_cmn_config()
1597 hdptx_write(hdptx, CMN_REG0075, 0x20); in hdptx_lcpll_ropll_cmn_config()
1598 hdptx_write(hdptx, CMN_REG0076, 0x30); in hdptx_lcpll_ropll_cmn_config()
1599 hdptx_write(hdptx, CMN_REG0077, 0x08); in hdptx_lcpll_ropll_cmn_config()
1600 hdptx_write(hdptx, CMN_REG0078, 0x0c); in hdptx_lcpll_ropll_cmn_config()
1601 hdptx_write(hdptx, CMN_REG007A, 0x00); in hdptx_lcpll_ropll_cmn_config()
1602 hdptx_write(hdptx, CMN_REG007B, 0x00); in hdptx_lcpll_ropll_cmn_config()
1603 hdptx_write(hdptx, CMN_REG007C, 0x00); in hdptx_lcpll_ropll_cmn_config()
1604 hdptx_write(hdptx, CMN_REG007D, 0x00); in hdptx_lcpll_ropll_cmn_config()
1605 hdptx_write(hdptx, CMN_REG007E, 0x00); in hdptx_lcpll_ropll_cmn_config()
1606 hdptx_write(hdptx, CMN_REG007F, 0x00); in hdptx_lcpll_ropll_cmn_config()
1607 hdptx_write(hdptx, CMN_REG0080, 0x00); in hdptx_lcpll_ropll_cmn_config()
1608 hdptx_write(hdptx, CMN_REG0081, 0x09); in hdptx_lcpll_ropll_cmn_config()
1609 hdptx_write(hdptx, CMN_REG0082, 0x04); in hdptx_lcpll_ropll_cmn_config()
1610 hdptx_write(hdptx, CMN_REG0083, 0x24); in hdptx_lcpll_ropll_cmn_config()
1611 hdptx_write(hdptx, CMN_REG0084, 0x20); in hdptx_lcpll_ropll_cmn_config()
1612 hdptx_write(hdptx, CMN_REG0085, 0x03); in hdptx_lcpll_ropll_cmn_config()
1613 hdptx_write(hdptx, CMN_REG0086, 0x11); in hdptx_lcpll_ropll_cmn_config()
1614 hdptx_write(hdptx, CMN_REG0087, 0x0c); in hdptx_lcpll_ropll_cmn_config()
1615 hdptx_write(hdptx, CMN_REG0089, 0x00); in hdptx_lcpll_ropll_cmn_config()
1616 hdptx_write(hdptx, CMN_REG008A, 0x55); in hdptx_lcpll_ropll_cmn_config()
1617 hdptx_write(hdptx, CMN_REG008B, 0x25); in hdptx_lcpll_ropll_cmn_config()
1618 hdptx_write(hdptx, CMN_REG008C, 0x2c); in hdptx_lcpll_ropll_cmn_config()
1619 hdptx_write(hdptx, CMN_REG008D, 0x22); in hdptx_lcpll_ropll_cmn_config()
1620 hdptx_write(hdptx, CMN_REG008E, 0x14); in hdptx_lcpll_ropll_cmn_config()
1621 hdptx_write(hdptx, CMN_REG008F, 0x20); in hdptx_lcpll_ropll_cmn_config()
1622 hdptx_write(hdptx, CMN_REG0090, 0x00); in hdptx_lcpll_ropll_cmn_config()
1623 hdptx_write(hdptx, CMN_REG0091, 0x00); in hdptx_lcpll_ropll_cmn_config()
1624 hdptx_write(hdptx, CMN_REG0092, 0x00); in hdptx_lcpll_ropll_cmn_config()
1625 hdptx_write(hdptx, CMN_REG0093, 0x00); in hdptx_lcpll_ropll_cmn_config()
1626 hdptx_write(hdptx, CMN_REG0095, 0x03); in hdptx_lcpll_ropll_cmn_config()
1627 hdptx_write(hdptx, CMN_REG0097, 0x00); in hdptx_lcpll_ropll_cmn_config()
1628 hdptx_write(hdptx, CMN_REG0099, 0x00); in hdptx_lcpll_ropll_cmn_config()
1629 hdptx_write(hdptx, CMN_REG009A, 0x11); in hdptx_lcpll_ropll_cmn_config()
1630 hdptx_write(hdptx, CMN_REG009B, 0x10); in hdptx_lcpll_ropll_cmn_config()
1632 hdptx_write(hdptx, CMN_REG009E, 0x03); in hdptx_lcpll_ropll_cmn_config()
1633 hdptx_write(hdptx, CMN_REG00A0, 0x60); in hdptx_lcpll_ropll_cmn_config()
1634 hdptx_write(hdptx, CMN_REG009F, 0xff); in hdptx_lcpll_ropll_cmn_config()
1642 hdptx_write(hdptx, SB_REG0114, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1643 hdptx_write(hdptx, SB_REG0115, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1644 hdptx_write(hdptx, SB_REG0116, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1645 hdptx_write(hdptx, SB_REG0117, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1646 hdptx_write(hdptx, LNTOP_REG0200, 0x04); in hdptx_lcpll_ropll_frl_mode_config()
1647 hdptx_write(hdptx, LNTOP_REG0201, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1648 hdptx_write(hdptx, LNTOP_REG0202, 0x00); in hdptx_lcpll_ropll_frl_mode_config()
1649 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); in hdptx_lcpll_ropll_frl_mode_config()
1650 hdptx_write(hdptx, LNTOP_REG0204, 0xff); in hdptx_lcpll_ropll_frl_mode_config()
1651 hdptx_write(hdptx, LNTOP_REG0205, 0xff); in hdptx_lcpll_ropll_frl_mode_config()
1652 hdptx_write(hdptx, LNTOP_REG0206, 0x05); in hdptx_lcpll_ropll_frl_mode_config()
1653 hdptx_write(hdptx, LANE_REG0303, 0x0c); in hdptx_lcpll_ropll_frl_mode_config()
1654 hdptx_write(hdptx, LANE_REG0307, 0x20); in hdptx_lcpll_ropll_frl_mode_config()
1655 hdptx_write(hdptx, LANE_REG030A, 0x17); in hdptx_lcpll_ropll_frl_mode_config()
1656 hdptx_write(hdptx, LANE_REG030B, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1657 hdptx_write(hdptx, LANE_REG030C, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1658 hdptx_write(hdptx, LANE_REG030D, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1659 hdptx_write(hdptx, LANE_REG030E, 0x38); in hdptx_lcpll_ropll_frl_mode_config()
1660 hdptx_write(hdptx, LANE_REG0310, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1661 hdptx_write(hdptx, LANE_REG0311, 0x0f); in hdptx_lcpll_ropll_frl_mode_config()
1662 hdptx_write(hdptx, LANE_REG0312, 0x3c); in hdptx_lcpll_ropll_frl_mode_config()
1663 hdptx_write(hdptx, LANE_REG0316, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1664 hdptx_write(hdptx, LANE_REG031B, 0x01); in hdptx_lcpll_ropll_frl_mode_config()
1665 hdptx_write(hdptx, LANE_REG031F, 0x15); in hdptx_lcpll_ropll_frl_mode_config()
1666 hdptx_write(hdptx, LANE_REG0320, 0xa0); in hdptx_lcpll_ropll_frl_mode_config()
1667 hdptx_write(hdptx, LANE_REG0403, 0x0c); in hdptx_lcpll_ropll_frl_mode_config()
1668 hdptx_write(hdptx, LANE_REG0407, 0x20); in hdptx_lcpll_ropll_frl_mode_config()
1669 hdptx_write(hdptx, LANE_REG040A, 0x17); in hdptx_lcpll_ropll_frl_mode_config()
1670 hdptx_write(hdptx, LANE_REG040B, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1671 hdptx_write(hdptx, LANE_REG040C, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1672 hdptx_write(hdptx, LANE_REG040D, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1673 hdptx_write(hdptx, LANE_REG040E, 0x38); in hdptx_lcpll_ropll_frl_mode_config()
1674 hdptx_write(hdptx, LANE_REG0410, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1675 hdptx_write(hdptx, LANE_REG0411, 0x0f); in hdptx_lcpll_ropll_frl_mode_config()
1676 hdptx_write(hdptx, LANE_REG0412, 0x3c); in hdptx_lcpll_ropll_frl_mode_config()
1677 hdptx_write(hdptx, LANE_REG0416, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1678 hdptx_write(hdptx, LANE_REG041B, 0x01); in hdptx_lcpll_ropll_frl_mode_config()
1679 hdptx_write(hdptx, LANE_REG041F, 0x15); in hdptx_lcpll_ropll_frl_mode_config()
1680 hdptx_write(hdptx, LANE_REG0420, 0xa0); in hdptx_lcpll_ropll_frl_mode_config()
1681 hdptx_write(hdptx, LANE_REG0503, 0x0c); in hdptx_lcpll_ropll_frl_mode_config()
1682 hdptx_write(hdptx, LANE_REG0507, 0x20); in hdptx_lcpll_ropll_frl_mode_config()
1683 hdptx_write(hdptx, LANE_REG050A, 0x17); in hdptx_lcpll_ropll_frl_mode_config()
1684 hdptx_write(hdptx, LANE_REG050B, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1685 hdptx_write(hdptx, LANE_REG050C, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1686 hdptx_write(hdptx, LANE_REG050D, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1687 hdptx_write(hdptx, LANE_REG0507, 0x20); in hdptx_lcpll_ropll_frl_mode_config()
1688 hdptx_write(hdptx, LANE_REG050A, 0x17); in hdptx_lcpll_ropll_frl_mode_config()
1689 hdptx_write(hdptx, LANE_REG050B, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1690 hdptx_write(hdptx, LANE_REG050C, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1691 hdptx_write(hdptx, LANE_REG050D, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1692 hdptx_write(hdptx, LANE_REG050E, 0x38); in hdptx_lcpll_ropll_frl_mode_config()
1693 hdptx_write(hdptx, LANE_REG0510, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1694 hdptx_write(hdptx, LANE_REG0511, 0x0f); in hdptx_lcpll_ropll_frl_mode_config()
1695 hdptx_write(hdptx, LANE_REG0512, 0x3c); in hdptx_lcpll_ropll_frl_mode_config()
1696 hdptx_write(hdptx, LANE_REG0516, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1697 hdptx_write(hdptx, LANE_REG051B, 0x01); in hdptx_lcpll_ropll_frl_mode_config()
1698 hdptx_write(hdptx, LANE_REG051F, 0x15); in hdptx_lcpll_ropll_frl_mode_config()
1699 hdptx_write(hdptx, LANE_REG0520, 0xa0); in hdptx_lcpll_ropll_frl_mode_config()
1700 hdptx_write(hdptx, LANE_REG0603, 0x0c); in hdptx_lcpll_ropll_frl_mode_config()
1701 hdptx_write(hdptx, LANE_REG0607, 0x20); in hdptx_lcpll_ropll_frl_mode_config()
1702 hdptx_write(hdptx, LANE_REG060A, 0x17); in hdptx_lcpll_ropll_frl_mode_config()
1703 hdptx_write(hdptx, LANE_REG060B, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1704 hdptx_write(hdptx, LANE_REG060C, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1705 hdptx_write(hdptx, LANE_REG060D, 0x77); in hdptx_lcpll_ropll_frl_mode_config()
1706 hdptx_write(hdptx, LANE_REG060E, 0x38); in hdptx_lcpll_ropll_frl_mode_config()
1707 hdptx_write(hdptx, LANE_REG0610, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1708 hdptx_write(hdptx, LANE_REG0611, 0x0f); in hdptx_lcpll_ropll_frl_mode_config()
1709 hdptx_write(hdptx, LANE_REG0612, 0x3c); in hdptx_lcpll_ropll_frl_mode_config()
1710 hdptx_write(hdptx, LANE_REG0616, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1711 hdptx_write(hdptx, LANE_REG061B, 0x01); in hdptx_lcpll_ropll_frl_mode_config()
1712 hdptx_write(hdptx, LANE_REG061F, 0x15); in hdptx_lcpll_ropll_frl_mode_config()
1713 hdptx_write(hdptx, LANE_REG0620, 0xa0); in hdptx_lcpll_ropll_frl_mode_config()
1715 hdptx_write(hdptx, LANE_REG031E, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1716 hdptx_write(hdptx, LANE_REG041E, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1717 hdptx_write(hdptx, LANE_REG051E, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1718 hdptx_write(hdptx, LANE_REG061E, 0x02); in hdptx_lcpll_ropll_frl_mode_config()
1720 hdptx_write(hdptx, LANE_REG0303, 0x2f); in hdptx_lcpll_ropll_frl_mode_config()
1721 hdptx_write(hdptx, LANE_REG0403, 0x2f); in hdptx_lcpll_ropll_frl_mode_config()
1722 hdptx_write(hdptx, LANE_REG0503, 0x2f); in hdptx_lcpll_ropll_frl_mode_config()
1723 hdptx_write(hdptx, LANE_REG0603, 0x2f); in hdptx_lcpll_ropll_frl_mode_config()
1724 hdptx_write(hdptx, LANE_REG0305, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1725 hdptx_write(hdptx, LANE_REG0405, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1726 hdptx_write(hdptx, LANE_REG0505, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1727 hdptx_write(hdptx, LANE_REG0605, 0x03); in hdptx_lcpll_ropll_frl_mode_config()
1728 hdptx_write(hdptx, LANE_REG0306, 0xfc); in hdptx_lcpll_ropll_frl_mode_config()
1729 hdptx_write(hdptx, LANE_REG0406, 0xfc); in hdptx_lcpll_ropll_frl_mode_config()
1730 hdptx_write(hdptx, LANE_REG0506, 0xfc); in hdptx_lcpll_ropll_frl_mode_config()
1731 hdptx_write(hdptx, LANE_REG0606, 0xfc); in hdptx_lcpll_ropll_frl_mode_config()
1733 hdptx_write(hdptx, LANE_REG0305, 0x4f); in hdptx_lcpll_ropll_frl_mode_config()
1734 hdptx_write(hdptx, LANE_REG0405, 0x4f); in hdptx_lcpll_ropll_frl_mode_config()
1735 hdptx_write(hdptx, LANE_REG0505, 0x4f); in hdptx_lcpll_ropll_frl_mode_config()
1736 hdptx_write(hdptx, LANE_REG0605, 0x4f); in hdptx_lcpll_ropll_frl_mode_config()
1737 hdptx_write(hdptx, LANE_REG0304, 0x14); in hdptx_lcpll_ropll_frl_mode_config()
1738 hdptx_write(hdptx, LANE_REG0404, 0x14); in hdptx_lcpll_ropll_frl_mode_config()
1739 hdptx_write(hdptx, LANE_REG0504, 0x14); in hdptx_lcpll_ropll_frl_mode_config()
1740 hdptx_write(hdptx, LANE_REG0604, 0x14); in hdptx_lcpll_ropll_frl_mode_config()
1748 hdptx_write(hdptx, LNTOP_REG0200, 0x04); in hdptx_lcpll_frl_mode_config()
1749 hdptx_write(hdptx, LNTOP_REG0201, 0x00); in hdptx_lcpll_frl_mode_config()
1750 hdptx_write(hdptx, LNTOP_REG0202, 0x00); in hdptx_lcpll_frl_mode_config()
1751 hdptx_write(hdptx, LNTOP_REG0203, 0xf0); in hdptx_lcpll_frl_mode_config()
1752 hdptx_write(hdptx, LNTOP_REG0204, 0xff); in hdptx_lcpll_frl_mode_config()
1753 hdptx_write(hdptx, LNTOP_REG0205, 0xff); in hdptx_lcpll_frl_mode_config()
1754 hdptx_write(hdptx, LNTOP_REG0206, 0x05); in hdptx_lcpll_frl_mode_config()
1755 hdptx_write(hdptx, LANE_REG0303, 0x0c); in hdptx_lcpll_frl_mode_config()
1756 hdptx_write(hdptx, LANE_REG0307, 0x20); in hdptx_lcpll_frl_mode_config()
1757 hdptx_write(hdptx, LANE_REG030A, 0x17); in hdptx_lcpll_frl_mode_config()
1758 hdptx_write(hdptx, LANE_REG030B, 0x77); in hdptx_lcpll_frl_mode_config()
1759 hdptx_write(hdptx, LANE_REG030C, 0x77); in hdptx_lcpll_frl_mode_config()
1760 hdptx_write(hdptx, LANE_REG030D, 0x77); in hdptx_lcpll_frl_mode_config()
1761 hdptx_write(hdptx, LANE_REG030E, 0x38); in hdptx_lcpll_frl_mode_config()
1762 hdptx_write(hdptx, LANE_REG0310, 0x03); in hdptx_lcpll_frl_mode_config()
1763 hdptx_write(hdptx, LANE_REG0311, 0x0f); in hdptx_lcpll_frl_mode_config()
1764 hdptx_write(hdptx, LANE_REG0312, 0x3c); in hdptx_lcpll_frl_mode_config()
1765 hdptx_write(hdptx, LANE_REG0316, 0x02); in hdptx_lcpll_frl_mode_config()
1766 hdptx_write(hdptx, LANE_REG031B, 0x01); in hdptx_lcpll_frl_mode_config()
1767 hdptx_write(hdptx, LANE_REG031F, 0x15); in hdptx_lcpll_frl_mode_config()
1768 hdptx_write(hdptx, LANE_REG0320, 0xa0); in hdptx_lcpll_frl_mode_config()
1769 hdptx_write(hdptx, LANE_REG0403, 0x0c); in hdptx_lcpll_frl_mode_config()
1770 hdptx_write(hdptx, LANE_REG0407, 0x20); in hdptx_lcpll_frl_mode_config()
1771 hdptx_write(hdptx, LANE_REG040A, 0x17); in hdptx_lcpll_frl_mode_config()
1772 hdptx_write(hdptx, LANE_REG040B, 0x77); in hdptx_lcpll_frl_mode_config()
1773 hdptx_write(hdptx, LANE_REG040C, 0x77); in hdptx_lcpll_frl_mode_config()
1774 hdptx_write(hdptx, LANE_REG040D, 0x77); in hdptx_lcpll_frl_mode_config()
1775 hdptx_write(hdptx, LANE_REG040E, 0x38); in hdptx_lcpll_frl_mode_config()
1776 hdptx_write(hdptx, LANE_REG0410, 0x03); in hdptx_lcpll_frl_mode_config()
1777 hdptx_write(hdptx, LANE_REG0411, 0x0f); in hdptx_lcpll_frl_mode_config()
1778 hdptx_write(hdptx, LANE_REG0412, 0x3c); in hdptx_lcpll_frl_mode_config()
1779 hdptx_write(hdptx, LANE_REG0416, 0x02); in hdptx_lcpll_frl_mode_config()
1780 hdptx_write(hdptx, LANE_REG041B, 0x01); in hdptx_lcpll_frl_mode_config()
1781 hdptx_write(hdptx, LANE_REG041F, 0x15); in hdptx_lcpll_frl_mode_config()
1782 hdptx_write(hdptx, LANE_REG0420, 0xa0); in hdptx_lcpll_frl_mode_config()
1783 hdptx_write(hdptx, LANE_REG0503, 0x0c); in hdptx_lcpll_frl_mode_config()
1784 hdptx_write(hdptx, LANE_REG0507, 0x20); in hdptx_lcpll_frl_mode_config()
1785 hdptx_write(hdptx, LANE_REG050A, 0x17); in hdptx_lcpll_frl_mode_config()
1786 hdptx_write(hdptx, LANE_REG050B, 0x77); in hdptx_lcpll_frl_mode_config()
1787 hdptx_write(hdptx, LANE_REG050C, 0x77); in hdptx_lcpll_frl_mode_config()
1788 hdptx_write(hdptx, LANE_REG050D, 0x77); in hdptx_lcpll_frl_mode_config()
1789 hdptx_write(hdptx, LANE_REG050E, 0x38); in hdptx_lcpll_frl_mode_config()
1790 hdptx_write(hdptx, LANE_REG0510, 0x03); in hdptx_lcpll_frl_mode_config()
1791 hdptx_write(hdptx, LANE_REG0511, 0x0f); in hdptx_lcpll_frl_mode_config()
1792 hdptx_write(hdptx, LANE_REG0512, 0x3c); in hdptx_lcpll_frl_mode_config()
1793 hdptx_write(hdptx, LANE_REG0516, 0x02); in hdptx_lcpll_frl_mode_config()
1794 hdptx_write(hdptx, LANE_REG051B, 0x01); in hdptx_lcpll_frl_mode_config()
1795 hdptx_write(hdptx, LANE_REG051F, 0x15); in hdptx_lcpll_frl_mode_config()
1796 hdptx_write(hdptx, LANE_REG0520, 0xa0); in hdptx_lcpll_frl_mode_config()
1797 hdptx_write(hdptx, LANE_REG0603, 0x0c); in hdptx_lcpll_frl_mode_config()
1798 hdptx_write(hdptx, LANE_REG0607, 0x20); in hdptx_lcpll_frl_mode_config()
1799 hdptx_write(hdptx, LANE_REG060A, 0x17); in hdptx_lcpll_frl_mode_config()
1800 hdptx_write(hdptx, LANE_REG060B, 0x77); in hdptx_lcpll_frl_mode_config()
1801 hdptx_write(hdptx, LANE_REG060C, 0x77); in hdptx_lcpll_frl_mode_config()
1802 hdptx_write(hdptx, LANE_REG060D, 0x77); in hdptx_lcpll_frl_mode_config()
1803 hdptx_write(hdptx, LANE_REG060E, 0x38); in hdptx_lcpll_frl_mode_config()
1804 hdptx_write(hdptx, LANE_REG0610, 0x03); in hdptx_lcpll_frl_mode_config()
1805 hdptx_write(hdptx, LANE_REG0611, 0x0f); in hdptx_lcpll_frl_mode_config()
1806 hdptx_write(hdptx, LANE_REG0612, 0x3c); in hdptx_lcpll_frl_mode_config()
1807 hdptx_write(hdptx, LANE_REG0616, 0x02); in hdptx_lcpll_frl_mode_config()
1808 hdptx_write(hdptx, LANE_REG061B, 0x01); in hdptx_lcpll_frl_mode_config()
1809 hdptx_write(hdptx, LANE_REG061F, 0x15); in hdptx_lcpll_frl_mode_config()
1810 hdptx_write(hdptx, LANE_REG0620, 0xa0); in hdptx_lcpll_frl_mode_config()
1812 hdptx_write(hdptx, LANE_REG031E, 0x02); in hdptx_lcpll_frl_mode_config()
1813 hdptx_write(hdptx, LANE_REG041E, 0x02); in hdptx_lcpll_frl_mode_config()
1814 hdptx_write(hdptx, LANE_REG051E, 0x02); in hdptx_lcpll_frl_mode_config()
1815 hdptx_write(hdptx, LANE_REG061E, 0x02); in hdptx_lcpll_frl_mode_config()
1817 hdptx_write(hdptx, LANE_REG0303, 0x2f); in hdptx_lcpll_frl_mode_config()
1818 hdptx_write(hdptx, LANE_REG0403, 0x2f); in hdptx_lcpll_frl_mode_config()
1819 hdptx_write(hdptx, LANE_REG0503, 0x2f); in hdptx_lcpll_frl_mode_config()
1820 hdptx_write(hdptx, LANE_REG0603, 0x2f); in hdptx_lcpll_frl_mode_config()
1821 hdptx_write(hdptx, LANE_REG0305, 0x03); in hdptx_lcpll_frl_mode_config()
1822 hdptx_write(hdptx, LANE_REG0405, 0x03); in hdptx_lcpll_frl_mode_config()
1823 hdptx_write(hdptx, LANE_REG0505, 0x03); in hdptx_lcpll_frl_mode_config()
1824 hdptx_write(hdptx, LANE_REG0605, 0x03); in hdptx_lcpll_frl_mode_config()
1825 hdptx_write(hdptx, LANE_REG0306, 0xfc); in hdptx_lcpll_frl_mode_config()
1826 hdptx_write(hdptx, LANE_REG0406, 0xfc); in hdptx_lcpll_frl_mode_config()
1827 hdptx_write(hdptx, LANE_REG0506, 0xfc); in hdptx_lcpll_frl_mode_config()
1828 hdptx_write(hdptx, LANE_REG0606, 0xfc); in hdptx_lcpll_frl_mode_config()
1830 hdptx_write(hdptx, LANE_REG0305, 0x4f); in hdptx_lcpll_frl_mode_config()
1831 hdptx_write(hdptx, LANE_REG0405, 0x4f); in hdptx_lcpll_frl_mode_config()
1832 hdptx_write(hdptx, LANE_REG0505, 0x4f); in hdptx_lcpll_frl_mode_config()
1833 hdptx_write(hdptx, LANE_REG0605, 0x4f); in hdptx_lcpll_frl_mode_config()
1834 hdptx_write(hdptx, LANE_REG0304, 0x14); in hdptx_lcpll_frl_mode_config()
1835 hdptx_write(hdptx, LANE_REG0404, 0x14); in hdptx_lcpll_frl_mode_config()
1836 hdptx_write(hdptx, LANE_REG0504, 0x14); in hdptx_lcpll_frl_mode_config()
1837 hdptx_write(hdptx, LANE_REG0604, 0x14); in hdptx_lcpll_frl_mode_config()
1848 printf("bus_width:0x%x,bit_rate:%d\n", bus_width, bit_rate); in rockchip_hdptx_phy_power_on()
1861 return 0; in rockchip_hdptx_phy_power_off()
1870 for (; cfg->bit_rate != ~0; cfg++) in rockchip_hdptx_phy_clk_round_rate()
1874 if (cfg->bit_rate == ~0 && !hdptx_phy_clk_pll_calc(bit_rate, NULL)) in rockchip_hdptx_phy_clk_round_rate()
1885 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; in rockchip_hdptx_phy_clk_set_rate()
1901 return 0; in rockchip_hdptx_phy_set_bus_width()
1928 if (hdptx->id < 0) in rockchip_hdptx_phy_hdmi_probe()
1929 hdptx->id = 0; in rockchip_hdptx_phy_hdmi_probe()
1961 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1967 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1973 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1979 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1985 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1991 if (ret < 0) { in rockchip_hdptx_phy_hdmi_probe()
1996 return 0; in rockchip_hdptx_phy_hdmi_probe()
2007 if (id < 0) in rockchip_hdptx_phy_hdmi_bind()
2008 id = 0; in rockchip_hdptx_phy_hdmi_bind()
2027 return 0; in rockchip_hdptx_phy_hdmi_bind()
2066 u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; in hdptx_clk_set_rate()
2103 return 0; in hdptx_clk_probe()