Lines Matching refs:FIELD_PREP
28 FIELD_PREP(NUM_LANES, priv->num_lanes - 1)); in max96755f_mipi_dsi_rx_config()
49 dm_i2c_reg_write(priv->dev, 0x0385, FIELD_PREP(DPI_HSYNC_WIDTH_L, hsa)); in max96755f_mipi_dsi_rx_config()
50 dm_i2c_reg_write(priv->dev, 0x0386, FIELD_PREP(DPI_VYSNC_WIDTH_L, vsa)); in max96755f_mipi_dsi_rx_config()
52 FIELD_PREP(DPI_VSYNC_WIDTH_H, (vsa >> 8)) | in max96755f_mipi_dsi_rx_config()
53 FIELD_PREP(DPI_HSYNC_WIDTH_H, (hsa >> 8))); in max96755f_mipi_dsi_rx_config()
54 dm_i2c_reg_write(priv->dev, 0x03a5, FIELD_PREP(DPI_VFP_L, vfp)); in max96755f_mipi_dsi_rx_config()
56 FIELD_PREP(DPI_VBP_L, vbp) | in max96755f_mipi_dsi_rx_config()
57 FIELD_PREP(DPI_VFP_H, (vfp >> 8))); in max96755f_mipi_dsi_rx_config()
58 dm_i2c_reg_write(priv->dev, 0x03a7, FIELD_PREP(DPI_VBP_H, (vbp >> 4))); in max96755f_mipi_dsi_rx_config()
59 dm_i2c_reg_write(priv->dev, 0x03a8, FIELD_PREP(DPI_VACT_L, vact)); in max96755f_mipi_dsi_rx_config()
60 dm_i2c_reg_write(priv->dev, 0x03a9, FIELD_PREP(DPI_VACT_H, (vact >> 8))); in max96755f_mipi_dsi_rx_config()
61 dm_i2c_reg_write(priv->dev, 0x03aa, FIELD_PREP(DPI_HFP_L, hfp)); in max96755f_mipi_dsi_rx_config()
63 FIELD_PREP(DPI_HBP_L, hbp) | in max96755f_mipi_dsi_rx_config()
64 FIELD_PREP(DPI_HFP_H, (hfp >> 7))); in max96755f_mipi_dsi_rx_config()
65 dm_i2c_reg_write(priv->dev, 0x03ac, FIELD_PREP(DPI_HBP_H, (hbp >> 4))); in max96755f_mipi_dsi_rx_config()
66 dm_i2c_reg_write(priv->dev, 0x03ad, FIELD_PREP(DPI_HACT_L, hact)); in max96755f_mipi_dsi_rx_config()
67 dm_i2c_reg_write(priv->dev, 0x03ae, FIELD_PREP(DPI_HACT_H, (hact >> 8))); in max96755f_mipi_dsi_rx_config()
79 FIELD_PREP(RESET_ONESHOT, 1) | in max96755f_bridge_enable()
80 FIELD_PREP(AUTO_LINK, 0) | in max96755f_bridge_enable()
81 FIELD_PREP(LINK_CFG, SPLITTER_MODE)); in max96755f_bridge_enable()
85 FIELD_PREP(TX_SPLIT_MASK_B, 0) | in max96755f_bridge_enable()
86 FIELD_PREP(TX_SPLIT_MASK_A, 1) | in max96755f_bridge_enable()
87 FIELD_PREP(TX_STR_SEL, 0)); in max96755f_bridge_enable()
90 FIELD_PREP(TX_SPLIT_MASK_B, 1) | in max96755f_bridge_enable()
91 FIELD_PREP(TX_SPLIT_MASK_A, 0) | in max96755f_bridge_enable()
92 FIELD_PREP(TX_STR_SEL, 1)); in max96755f_bridge_enable()
95 FIELD_PREP(DV_SWP_AB, priv->dv_swp_ab) | in max96755f_bridge_enable()
96 FIELD_PREP(DV_CONV, 1) | in max96755f_bridge_enable()
97 FIELD_PREP(DV_SPL, 1) | in max96755f_bridge_enable()
98 FIELD_PREP(DV_EN, 1)); in max96755f_bridge_enable()
101 FIELD_PREP(START_PORTAX, 1) | in max96755f_bridge_enable()
102 FIELD_PREP(START_PORTAY, 1)); in max96755f_bridge_enable()
105 FIELD_PREP(VID_TX_EN_X, 1) | in max96755f_bridge_enable()
106 FIELD_PREP(VID_TX_EN_Y, 1)); in max96755f_bridge_enable()
110 FIELD_PREP(VID_TX_EN_X, 1)); in max96755f_bridge_enable()
112 FIELD_PREP(START_PORTAX, 1)); in max96755f_bridge_enable()
116 FIELD_PREP(RESET_ONESHOT, 1)); in max96755f_bridge_enable()
126 FIELD_PREP(VID_TX_EN_X, 0)); in max96755f_bridge_disable()
131 FIELD_PREP(AUTO_LINK, 0) | in max96755f_bridge_disable()
132 FIELD_PREP(LINK_CFG, LINKA)); in max96755f_bridge_disable()