299 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val)  in dsi_write()  argument
301 	writel(val, dsi2->base + reg);  in dsi_write()
304 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg)  in dsi_read()  argument
306 	return readl(dsi2->base + reg);  in dsi_read()
309 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2,  in dsi_update_bits()  argument
314 	orig = dsi_read(dsi2, reg);  in dsi_update_bits()
317 	dsi_write(dsi2, reg, tmp);  in dsi_update_bits()
320 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index,  in grf_field_write()  argument
323 	const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] :  in grf_field_write()
324 			  dsi2->pdata->dsi0_grf_reg_fields[index];  in grf_field_write()
335 	regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb);  in grf_field_write()
338 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_get_lane_rate()  argument
340 	const struct drm_display_mode *mode = &dsi2->mode;  in dw_mipi_dsi2_get_lane_rate()
346 	max_lane_rate = (dsi2->c_option) ?  in dw_mipi_dsi2_get_lane_rate()
347 			dsi2->pdata->cphy_max_symbol_rate_per_lane :  in dw_mipi_dsi2_get_lane_rate()
348 			dsi2->pdata->dphy_max_bit_rate_per_lane;  in dw_mipi_dsi2_get_lane_rate()
354 	value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0);  in dw_mipi_dsi2_get_lane_rate()
360 	bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format);  in dw_mipi_dsi2_get_lane_rate()
364 	lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes;  in dw_mipi_dsi2_get_lane_rate()
368 	if (dsi2->c_option)  in dw_mipi_dsi2_get_lane_rate()
376 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {  in dw_mipi_dsi2_get_lane_rate()
389 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2)  in cri_fifos_wait_avail()  argument
395 	ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS,  in cri_fifos_wait_avail()
406 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2,  in dw_mipi_dsi2_read_from_fifo()  argument
413 	unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode);  in dw_mipi_dsi2_read_from_fifo()
416 	ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS,  in dw_mipi_dsi2_read_from_fifo()
424 	val = dsi_read(dsi2, DSI2_CRI_RX_HDR);  in dw_mipi_dsi2_read_from_fifo()
437 		val = dsi_read(dsi2, DSI2_CRI_RX_PLD);  in dw_mipi_dsi2_read_from_fifo()
445 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2,  in dw_mipi_dsi2_transfer()  argument
453 	dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN,  in dw_mipi_dsi2_transfer()
465 	ret = cri_fifos_wait_avail(dsi2);  in dw_mipi_dsi2_transfer()
475 			dsi_write(dsi2, DSI2_CRI_TX_PLD, val);  in dw_mipi_dsi2_transfer()
479 			dsi_write(dsi2, DSI2_CRI_TX_PLD, val);  in dw_mipi_dsi2_transfer()
488 	dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val);  in dw_mipi_dsi2_transfer()
490 	ret = cri_fifos_wait_avail(dsi2);  in dw_mipi_dsi2_transfer()
495 		ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg);  in dw_mipi_dsi2_transfer()
500 	if (dsi2->slave) {  in dw_mipi_dsi2_transfer()
501 		ret = dw_mipi_dsi2_transfer(dsi2->slave, msg);  in dw_mipi_dsi2_transfer()
509 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_ipi_color_coding_cfg()  argument
513 	switch (dsi2->format) {  in dw_mipi_dsi2_ipi_color_coding_cfg()
528 	      IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB);  in dw_mipi_dsi2_ipi_color_coding_cfg()
529 	dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val);  in dw_mipi_dsi2_ipi_color_coding_cfg()
530 	grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth);  in dw_mipi_dsi2_ipi_color_coding_cfg()
532 	if (dsi2->dsc_enable)  in dw_mipi_dsi2_ipi_color_coding_cfg()
533 		grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC);  in dw_mipi_dsi2_ipi_color_coding_cfg()
536 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_ipi_set()  argument
538 	struct drm_display_mode *mode = &dsi2->mode;  in dw_mipi_dsi2_ipi_set()
545 	if (dsi2->slave || dsi2->master)  in dw_mipi_dsi2_ipi_set()
550 	dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));  in dw_mipi_dsi2_ipi_set()
552 	dw_mipi_dsi2_ipi_color_coding_cfg(dsi2);  in dw_mipi_dsi2_ipi_set()
558 	if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))  in dw_mipi_dsi2_ipi_set()
572 	if (dsi2->c_option)  in dw_mipi_dsi2_ipi_set()
573 		phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);  in dw_mipi_dsi2_ipi_set()
575 		phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);  in dw_mipi_dsi2_ipi_set()
579 	dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time));  in dw_mipi_dsi2_ipi_set()
583 	dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time));  in dw_mipi_dsi2_ipi_set()
587 	dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time));  in dw_mipi_dsi2_ipi_set()
591 	dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time));  in dw_mipi_dsi2_ipi_set()
593 	dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa));  in dw_mipi_dsi2_ipi_set()
594 	dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp));  in dw_mipi_dsi2_ipi_set()
595 	dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact));  in dw_mipi_dsi2_ipi_set()
596 	dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp));  in dw_mipi_dsi2_ipi_set()
599 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_set_vid_mode()  argument
604 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)  in dw_mipi_dsi2_set_vid_mode()
607 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)  in dw_mipi_dsi2_set_vid_mode()
610 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)  in dw_mipi_dsi2_set_vid_mode()
613 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)  in dw_mipi_dsi2_set_vid_mode()
615 	else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)  in dw_mipi_dsi2_set_vid_mode()
620 	dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val);  in dw_mipi_dsi2_set_vid_mode()
622 	dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE);  in dw_mipi_dsi2_set_vid_mode()
623 	ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS,  in dw_mipi_dsi2_set_vid_mode()
630 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_set_data_stream_mode()  argument
635 	dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE);  in dw_mipi_dsi2_set_data_stream_mode()
636 	ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS,  in dw_mipi_dsi2_set_data_stream_mode()
643 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_set_cmd_mode()  argument
648 	dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE);  in dw_mipi_dsi2_set_cmd_mode()
649 	ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS,  in dw_mipi_dsi2_set_cmd_mode()
656 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_enable()  argument
658 	dw_mipi_dsi2_ipi_set(dsi2);  in dw_mipi_dsi2_enable()
660 	if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)  in dw_mipi_dsi2_enable()
661 		dw_mipi_dsi2_set_vid_mode(dsi2);  in dw_mipi_dsi2_enable()
663 		dw_mipi_dsi2_set_data_stream_mode(dsi2);  in dw_mipi_dsi2_enable()
665 	if (dsi2->slave)  in dw_mipi_dsi2_enable()
666 		dw_mipi_dsi2_enable(dsi2->slave);  in dw_mipi_dsi2_enable()
669 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_disable()  argument
671 	dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0);  in dw_mipi_dsi2_disable()
672 	dw_mipi_dsi2_set_cmd_mode(dsi2);  in dw_mipi_dsi2_disable()
674 	if (dsi2->slave)  in dw_mipi_dsi2_disable()
675 		dw_mipi_dsi2_disable(dsi2->slave);  in dw_mipi_dsi2_disable()
678 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_post_disable()  argument
680 	if (!dsi2->prepared)  in dw_mipi_dsi2_post_disable()
683 	dsi_write(dsi2, DSI2_PWR_UP, RESET);  in dw_mipi_dsi2_post_disable()
685 	if (dsi2->dcphy.phy)  in dw_mipi_dsi2_post_disable()
686 		rockchip_phy_power_off(dsi2->dcphy.phy);  in dw_mipi_dsi2_post_disable()
688 	dsi2->prepared = false;  in dw_mipi_dsi2_post_disable()
690 	if (dsi2->slave)  in dw_mipi_dsi2_post_disable()
691 		dw_mipi_dsi2_post_disable(dsi2->slave);  in dw_mipi_dsi2_post_disable()
698 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_pre_init()  local
699 	struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev);  in dw_mipi_dsi2_connector_pre_init()
719 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_get_dsc_params_from_sink()  argument
721 	struct udevice *dev = dsi2->device->dev;  in dw_mipi_dsi2_get_dsc_params_from_sink()
728 	dsi2->c_option = dev_read_bool(dev, "phy-c-option");  in dw_mipi_dsi2_get_dsc_params_from_sink()
729 	dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable");  in dw_mipi_dsi2_get_dsc_params_from_sink()
730 	dsi2->dsc_enable = dev_read_bool(dev, "compressed-data");  in dw_mipi_dsi2_get_dsc_params_from_sink()
732 	if (dsi2->slave) {  in dw_mipi_dsi2_get_dsc_params_from_sink()
733 		dsi2->slave->c_option = dsi2->c_option;  in dw_mipi_dsi2_get_dsc_params_from_sink()
734 		dsi2->slave->scrambling_en = dsi2->scrambling_en;  in dw_mipi_dsi2_get_dsc_params_from_sink()
735 		dsi2->slave->dsc_enable = dsi2->dsc_enable;  in dw_mipi_dsi2_get_dsc_params_from_sink()
738 	dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0);  in dw_mipi_dsi2_get_dsc_params_from_sink()
739 	dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0);  in dw_mipi_dsi2_get_dsc_params_from_sink()
740 	dsi2->version_major = dev_read_u32_default(dev, "version-major", 0);  in dw_mipi_dsi2_get_dsc_params_from_sink()
741 	dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0);  in dw_mipi_dsi2_get_dsc_params_from_sink()
769 	dsi2->pps = pps;  in dw_mipi_dsi2_get_dsc_params_from_sink()
778 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_init()  local
784 	conn_state->disp_info  = rockchip_get_disp_info(conn_state->type, dsi2->id);  in dw_mipi_dsi2_connector_init()
785 	dsi2->dcphy.phy = conn->phy;  in dw_mipi_dsi2_connector_init()
790 		dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;  in dw_mipi_dsi2_connector_init()
792 	if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {  in dw_mipi_dsi2_connector_init()
797 	if (dsi2->lanes > 4) {  in dw_mipi_dsi2_connector_init()
804 		dsi2->slave = dev_get_priv(dev);  in dw_mipi_dsi2_connector_init()
805 		if (!dsi2->slave)  in dw_mipi_dsi2_connector_init()
808 		dsi2->slave->master = dsi2;  in dw_mipi_dsi2_connector_init()
809 		dsi2->lanes /= 2;  in dw_mipi_dsi2_connector_init()
810 		dsi2->slave->lanes = dsi2->lanes;  in dw_mipi_dsi2_connector_init()
811 		dsi2->slave->format = dsi2->format;  in dw_mipi_dsi2_connector_init()
812 		dsi2->slave->mode_flags = dsi2->mode_flags;  in dw_mipi_dsi2_connector_init()
813 		dsi2->slave->channel = dsi2->channel;  in dw_mipi_dsi2_connector_init()
816 		if (dsi2->data_swap)  in dw_mipi_dsi2_connector_init()
830 		dsi2->slave->dcphy.phy = phy;  in dw_mipi_dsi2_connector_init()
835 	dw_mipi_dsi2_get_dsc_params_from_sink(dsi2);  in dw_mipi_dsi2_connector_init()
837 	if (dm_gpio_is_valid(&dsi2->te_gpio)) {  in dw_mipi_dsi2_connector_init()
839 		conn_state->te_gpio = &dsi2->te_gpio;  in dw_mipi_dsi2_connector_init()
842 	if (dsi2->dsc_enable) {  in dw_mipi_dsi2_connector_init()
844 		cstate->dsc_sink_cap.version_major = dsi2->version_major;  in dw_mipi_dsi2_connector_init()
845 		cstate->dsc_sink_cap.version_minor = dsi2->version_minor;  in dw_mipi_dsi2_connector_init()
846 		cstate->dsc_sink_cap.slice_width = dsi2->slice_width;  in dw_mipi_dsi2_connector_init()
847 		cstate->dsc_sink_cap.slice_height = dsi2->slice_height;  in dw_mipi_dsi2_connector_init()
851 		memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set));  in dw_mipi_dsi2_connector_init()
912 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate)  in dw_mipi_dsi2_set_hs_clk()  argument
914 	mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg);  in dw_mipi_dsi2_set_hs_clk()
916 	if (!dsi2->c_option)  in dw_mipi_dsi2_set_hs_clk()
917 		rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY);  in dw_mipi_dsi2_set_hs_clk()
919 	rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate);  in dw_mipi_dsi2_set_hs_clk()
920 	dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC);  in dw_mipi_dsi2_set_hs_clk()
923 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_host_softrst()  argument
925 	dsi_write(dsi2, DSI2_SOFT_RESET, 0X0);  in dw_mipi_dsi2_host_softrst()
927 	dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN);  in dw_mipi_dsi2_host_softrst()
931 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode)  in dw_mipi_dsi2_work_mode()  argument
938 	dsi_write(dsi2, MANUAL_MODE_CFG, mode);  in dw_mipi_dsi2_work_mode()
941 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_phy_mode_cfg()  argument
946 	val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes);  in dw_mipi_dsi2_phy_mode_cfg()
947 	val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY);  in dw_mipi_dsi2_phy_mode_cfg()
948 	dsi_write(dsi2, DSI2_PHY_MODE_CFG, val);  in dw_mipi_dsi2_phy_mode_cfg()
951 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_phy_clk_mode_cfg()  argument
957 	if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)  in dw_mipi_dsi2_phy_clk_mode_cfg()
964 	dsi_write(dsi2, DSI2_PHY_CLK_CFG, val);  in dw_mipi_dsi2_phy_clk_mode_cfg()
967 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_phy_ratio_cfg()  argument
969 	struct drm_display_mode *mode = &dsi2->mode;  in dw_mipi_dsi2_phy_ratio_cfg()
977 	if (dsi2->c_option)  in dw_mipi_dsi2_phy_ratio_cfg()
978 		phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);  in dw_mipi_dsi2_phy_ratio_cfg()
981 		phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);  in dw_mipi_dsi2_phy_ratio_cfg()
988 	dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp));  in dw_mipi_dsi2_phy_ratio_cfg()
992 	dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp));  in dw_mipi_dsi2_phy_ratio_cfg()
995 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()  argument
997 	struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg;  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1001 	hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1009 	dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp));  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1014 	dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp));  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1017 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_phy_init()  argument
1019 	dw_mipi_dsi2_phy_mode_cfg(dsi2);  in dw_mipi_dsi2_phy_init()
1020 	dw_mipi_dsi2_phy_clk_mode_cfg(dsi2);  in dw_mipi_dsi2_phy_init()
1021 	dw_mipi_dsi2_phy_ratio_cfg(dsi2);  in dw_mipi_dsi2_phy_init()
1022 	dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2);  in dw_mipi_dsi2_phy_init()
1027 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_tx_option_set()  argument
1033 	if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET)  in dw_mipi_dsi2_tx_option_set()
1036 	dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val);  in dw_mipi_dsi2_tx_option_set()
1037 	dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));  in dw_mipi_dsi2_tx_option_set()
1039 	if (dsi2->scrambling_en)  in dw_mipi_dsi2_tx_option_set()
1040 		dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN);  in dw_mipi_dsi2_tx_option_set()
1043 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable)  in dw_mipi_dsi2_irq_enable()  argument
1046 		dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1);  in dw_mipi_dsi2_irq_enable()
1047 		dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf);  in dw_mipi_dsi2_irq_enable()
1048 		dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1);  in dw_mipi_dsi2_irq_enable()
1049 		dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1);  in dw_mipi_dsi2_irq_enable()
1050 		dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1);  in dw_mipi_dsi2_irq_enable()
1051 		dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1);  in dw_mipi_dsi2_irq_enable()
1052 		dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1);  in dw_mipi_dsi2_irq_enable()
1054 		dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0);  in dw_mipi_dsi2_irq_enable()
1055 		dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0);  in dw_mipi_dsi2_irq_enable()
1056 		dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0);  in dw_mipi_dsi2_irq_enable()
1057 		dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0);  in dw_mipi_dsi2_irq_enable()
1058 		dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0);  in dw_mipi_dsi2_irq_enable()
1059 		dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0);  in dw_mipi_dsi2_irq_enable()
1060 		dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0);  in dw_mipi_dsi2_irq_enable()
1064 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2)  in mipi_dcphy_power_on()  argument
1066 	if (!dsi2->dcphy.phy)  in mipi_dcphy_power_on()
1069 	rockchip_phy_power_on(dsi2->dcphy.phy);  in mipi_dcphy_power_on()
1072 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)  in dw_mipi_dsi2_pre_enable()  argument
1074 	if (dsi2->prepared)  in dw_mipi_dsi2_pre_enable()
1077 	dw_mipi_dsi2_host_softrst(dsi2);  in dw_mipi_dsi2_pre_enable()
1078 	dsi_write(dsi2, DSI2_PWR_UP, RESET);  in dw_mipi_dsi2_pre_enable()
1080 	dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN);  in dw_mipi_dsi2_pre_enable()
1081 	dw_mipi_dsi2_phy_init(dsi2);  in dw_mipi_dsi2_pre_enable()
1082 	dw_mipi_dsi2_tx_option_set(dsi2);  in dw_mipi_dsi2_pre_enable()
1083 	dw_mipi_dsi2_irq_enable(dsi2, 0);  in dw_mipi_dsi2_pre_enable()
1084 	mipi_dcphy_power_on(dsi2);  in dw_mipi_dsi2_pre_enable()
1085 	dsi_write(dsi2, DSI2_PWR_UP, POWER_UP);  in dw_mipi_dsi2_pre_enable()
1086 	dw_mipi_dsi2_set_cmd_mode(dsi2);  in dw_mipi_dsi2_pre_enable()
1088 	dsi2->prepared = true;  in dw_mipi_dsi2_pre_enable()
1090 	if (dsi2->slave)  in dw_mipi_dsi2_pre_enable()
1091 		dw_mipi_dsi2_pre_enable(dsi2->slave);  in dw_mipi_dsi2_pre_enable()
1097 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_prepare()  local
1101 	memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode));  in dw_mipi_dsi2_connector_prepare()
1102 	if (dsi2->slave)  in dw_mipi_dsi2_connector_prepare()
1103 		memcpy(&dsi2->slave->mode, &dsi2->mode,  in dw_mipi_dsi2_connector_prepare()
1106 	lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2);  in dw_mipi_dsi2_connector_prepare()
1107 	if (dsi2->dcphy.phy)  in dw_mipi_dsi2_connector_prepare()
1108 		dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate);  in dw_mipi_dsi2_connector_prepare()
1110 	if (dsi2->slave && dsi2->slave->dcphy.phy)  in dw_mipi_dsi2_connector_prepare()
1111 		dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate);  in dw_mipi_dsi2_connector_prepare()
1114 	       dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps",  in dw_mipi_dsi2_connector_prepare()
1115 	       dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes);  in dw_mipi_dsi2_connector_prepare()
1117 	dw_mipi_dsi2_pre_enable(dsi2);  in dw_mipi_dsi2_connector_prepare()
1125 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_unprepare()  local
1127 	dw_mipi_dsi2_post_disable(dsi2);  in dw_mipi_dsi2_connector_unprepare()
1133 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_enable()  local
1135 	dw_mipi_dsi2_enable(dsi2);  in dw_mipi_dsi2_connector_enable()
1143 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_disable()  local
1145 	dw_mipi_dsi2_disable(dsi2);  in dw_mipi_dsi2_connector_disable()
1153 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);  in dw_mipi_dsi2_connector_mode_valid()  local
1155 	u8 min_pixels = dsi2->slave ? 8 : 4;  in dw_mipi_dsi2_connector_mode_valid()
1197 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev);  in dw_mipi_dsi2_probe()  local
1203 	dsi2->base = dev_read_addr_ptr(dev);  in dw_mipi_dsi2_probe()
1208 		dsi2->grf = syscon_get_regmap(syscon);  in dw_mipi_dsi2_probe()
1209 		if (!dsi2->grf)  in dw_mipi_dsi2_probe()
1218 				   &dsi2->te_gpio, GPIOD_IS_IN);  in dw_mipi_dsi2_probe()
1224 	dsi2->dev = dev;  in dw_mipi_dsi2_probe()
1225 	dsi2->pdata = pdata;  in dw_mipi_dsi2_probe()
1226 	dsi2->id = id;  in dw_mipi_dsi2_probe()
1227 	dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap");  in dw_mipi_dsi2_probe()
1229 	rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL,  in dw_mipi_dsi2_probe()
1271 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev);  in dw_mipi_dsi2_host_transfer()  local
1273 	return dw_mipi_dsi2_transfer(dsi2, msg);  in dw_mipi_dsi2_host_transfer()
1279 	struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev);  in dw_mipi_dsi2_host_attach()  local
1284 	dsi2->lanes = device->lanes;  in dw_mipi_dsi2_host_attach()
1285 	dsi2->channel = device->channel;  in dw_mipi_dsi2_host_attach()
1286 	dsi2->format = device->format;  in dw_mipi_dsi2_host_attach()
1287 	dsi2->mode_flags = device->mode_flags;  in dw_mipi_dsi2_host_attach()
1288 	dsi2->device = device;  in dw_mipi_dsi2_host_attach()