254 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)  in dsi_write()  argument
256 	writel(val, dsi->base + reg);  in dsi_write()
259 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)  in dsi_read()  argument
261 	return readl(dsi->base + reg);  in dsi_read()
264 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi,  in dsi_update_bits()  argument
269 	orig = dsi_read(dsi, reg);  in dsi_update_bits()
272 	dsi_write(dsi, reg, tmp);  in dsi_update_bits()
275 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index,  in grf_field_write()  argument
278 	const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] :  in grf_field_write()
279 			  dsi->pdata->dsi0_grf_reg_fields[index];  in grf_field_write()
290 	rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb);  in grf_field_write()
293 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi)  in dpishutdn_assert()  argument
295 	grf_field_write(dsi, DPISHUTDN, 1);  in dpishutdn_assert()
298 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi)  in dpishutdn_deassert()  argument
300 	grf_field_write(dsi, DPISHUTDN, 0);  in dpishutdn_deassert()
303 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)  in genif_wait_w_pld_fifo_not_full()  argument
308 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_w_pld_fifo_not_full()
319 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)  in genif_wait_cmd_fifo_not_full()  argument
324 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_cmd_fifo_not_full()
335 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)  in genif_wait_write_fifo_empty()  argument
342 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_write_fifo_empty()
353 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_enableclk_assert()  argument
355 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);  in mipi_dphy_enableclk_assert()
359 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_enableclk_deassert()  argument
361 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);  in mipi_dphy_enableclk_deassert()
365 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_shutdownz_assert()  argument
367 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);  in mipi_dphy_shutdownz_assert()
371 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_shutdownz_deassert()  argument
373 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);  in mipi_dphy_shutdownz_deassert()
377 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_rstz_assert()  argument
379 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0);  in mipi_dphy_rstz_assert()
383 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_rstz_deassert()  argument
385 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);  in mipi_dphy_rstz_deassert()
389 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi)  in testif_testclk_assert()  argument
391 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);  in testif_testclk_assert()
395 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi)  in testif_testclk_deassert()  argument
397 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0);  in testif_testclk_deassert()
401 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi)  in testif_testclr_assert()  argument
403 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);  in testif_testclr_assert()
407 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi)  in testif_testclr_deassert()  argument
409 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0);  in testif_testclr_deassert()
413 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi)  in testif_testen_assert()  argument
415 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);  in testif_testen_assert()
419 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi)  in testif_testen_deassert()  argument
421 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0);  in testif_testen_deassert()
425 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data)  in testif_set_data()  argument
427 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1,  in testif_set_data()
432 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi)  in testif_get_data()  argument
434 	return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT;  in testif_get_data()
437 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code)  in testif_test_code_write()  argument
439 	testif_testclk_assert(dsi);  in testif_test_code_write()
440 	testif_set_data(dsi, test_code);  in testif_test_code_write()
441 	testif_testen_assert(dsi);  in testif_test_code_write()
442 	testif_testclk_deassert(dsi);  in testif_test_code_write()
443 	testif_testen_deassert(dsi);  in testif_test_code_write()
446 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data)  in testif_test_data_write()  argument
448 	testif_testclk_deassert(dsi);  in testif_test_data_write()
449 	testif_set_data(dsi, test_data);  in testif_test_data_write()
450 	testif_testclk_assert(dsi);  in testif_test_data_write()
453 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data)  in testif_write()  argument
455 	testif_test_code_write(dsi, test_code);  in testif_write()
456 	testif_test_data_write(dsi, test_data);  in testif_write()
458 	dev_dbg(dsi->dev,  in testif_write()
460 		test_code, test_data, testif_get_data(dsi));  in testif_write()
463 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)  in mipi_dphy_power_on()  argument
468 	mipi_dphy_shutdownz_deassert(dsi);  in mipi_dphy_power_on()
469 	mipi_dphy_rstz_deassert(dsi);  in mipi_dphy_power_on()
472 	if (dsi->dphy.phy) {  in mipi_dphy_power_on()
473 		rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY);  in mipi_dphy_power_on()
474 		rockchip_phy_power_on(dsi->dphy.phy);  in mipi_dphy_power_on()
477 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,  in mipi_dphy_power_on()
480 		dev_err(dsi->dev, "PHY is not locked\n");  in mipi_dphy_power_on()
487 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,  in mipi_dphy_power_on()
491 		dev_err(dsi->dev, "lane module is not in stop state\n");  in mipi_dphy_power_on()
500 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_phy_init()  argument
523 		if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)  in dw_mipi_dsi_phy_init()
530 	testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange));  in dw_mipi_dsi_phy_init()
532 	txbyteclkhs = dsi->lane_mbps >> 3;  in dw_mipi_dsi_phy_init()
534 	testif_write(dsi, 0x60, 0x80 | counter);  in dw_mipi_dsi_phy_init()
535 	testif_write(dsi, 0x70, 0x80 | counter);  in dw_mipi_dsi_phy_init()
537 	n = dsi->dphy.input_div - 1;  in dw_mipi_dsi_phy_init()
538 	m = dsi->dphy.feedback_div - 1;  in dw_mipi_dsi_phy_init()
539 	testif_write(dsi, 0x19, 0x30);  in dw_mipi_dsi_phy_init()
540 	testif_write(dsi, 0x17, INPUT_DIV(n));  in dw_mipi_dsi_phy_init()
541 	testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m));  in dw_mipi_dsi_phy_init()
542 	testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5));  in dw_mipi_dsi_phy_init()
545 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_get_lane_rate()  argument
547 	const struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_get_lane_rate()
548 	unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane;  in dw_mipi_dsi_get_lane_rate()
555 	value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0);  in dw_mipi_dsi_get_lane_rate()
559 	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in dw_mipi_dsi_get_lane_rate()
563 	lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;  in dw_mipi_dsi_get_lane_rate()
579 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate)  in dw_mipi_dsi_set_pll()  argument
637 	dsi->lane_mbps = best_freq / 1000 / 1000;  in dw_mipi_dsi_set_pll()
638 	dsi->dphy.input_div = best_prediv;  in dw_mipi_dsi_set_pll()
639 	dsi->dphy.feedback_div = best_fbdiv;  in dw_mipi_dsi_set_pll()
640 	if (dsi->slave) {  in dw_mipi_dsi_set_pll()
641 		dsi->slave->lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_set_pll()
642 		dsi->slave->dphy.input_div = dsi->dphy.input_div;  in dw_mipi_dsi_set_pll()
643 		dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div;  in dw_mipi_dsi_set_pll()
645 	if (dsi->master) {  in dw_mipi_dsi_set_pll()
646 		dsi->master->lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_set_pll()
647 		dsi->master->dphy.input_div = dsi->dphy.input_div;  in dw_mipi_dsi_set_pll()
648 		dsi->master->dphy.feedback_div = dsi->dphy.feedback_div;  in dw_mipi_dsi_set_pll()
652 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_read_from_fifo()  argument
660 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read_from_fifo()
669 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read_from_fifo()
676 		val = dsi_read(dsi, DSI_GEN_PLD_DATA);  in dw_mipi_dsi_read_from_fifo()
700 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_turn_on_peripheral()  argument
702 	dpishutdn_assert(dsi);  in dw_mipi_dsi_turn_on_peripheral()
704 	dpishutdn_deassert(dsi);  in dw_mipi_dsi_turn_on_peripheral()
709 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_shutdown_peripheral()  argument
711 	dpishutdn_deassert(dsi);  in dw_mipi_dsi_shutdown_peripheral()
713 	dpishutdn_assert(dsi);  in dw_mipi_dsi_shutdown_peripheral()
718 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_transfer()  argument
726 		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);  in dw_mipi_dsi_transfer()
727 		dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0);  in dw_mipi_dsi_transfer()
729 		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0);  in dw_mipi_dsi_transfer()
730 		dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_transfer()
736 		return dw_mipi_dsi_shutdown_peripheral(dsi);  in dw_mipi_dsi_transfer()
738 		return dw_mipi_dsi_turn_on_peripheral(dsi);  in dw_mipi_dsi_transfer()
740 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,  in dw_mipi_dsi_transfer()
741 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
745 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,  in dw_mipi_dsi_transfer()
746 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
750 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,  in dw_mipi_dsi_transfer()
751 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
755 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,  in dw_mipi_dsi_transfer()
756 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
760 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE,  in dw_mipi_dsi_transfer()
761 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
765 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,  in dw_mipi_dsi_transfer()
766 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
770 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,  in dw_mipi_dsi_transfer()
771 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
775 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,  in dw_mipi_dsi_transfer()
776 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
780 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,  in dw_mipi_dsi_transfer()
781 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
785 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,  in dw_mipi_dsi_transfer()
786 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
790 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,  in dw_mipi_dsi_transfer()
791 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
795 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,  in dw_mipi_dsi_transfer()
796 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
804 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG,  in dw_mipi_dsi_transfer()
807 	/* create a packet to the DSI protocol */  in dw_mipi_dsi_transfer()
825 		ret = genif_wait_w_pld_fifo_not_full(dsi);  in dw_mipi_dsi_transfer()
833 			dsi_write(dsi, DSI_GEN_PLD_DATA, val);  in dw_mipi_dsi_transfer()
837 			dsi_write(dsi, DSI_GEN_PLD_DATA, val);  in dw_mipi_dsi_transfer()
843 	ret = genif_wait_cmd_fifo_not_full(dsi);  in dw_mipi_dsi_transfer()
849 	dsi_write(dsi, DSI_GEN_HDR, val);  in dw_mipi_dsi_transfer()
851 	ret = genif_wait_write_fifo_empty(dsi);  in dw_mipi_dsi_transfer()
856 		ret = dw_mipi_dsi_read_from_fifo(dsi, msg);  in dw_mipi_dsi_transfer()
861 	if (dsi->slave) {  in dw_mipi_dsi_transfer()
862 		ret = dw_mipi_dsi_transfer(dsi->slave, msg);  in dw_mipi_dsi_transfer()
870 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_video_mode_config()  argument
875 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)  in dw_mipi_dsi_video_mode_config()
878 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)  in dw_mipi_dsi_video_mode_config()
881 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)  in dw_mipi_dsi_video_mode_config()
883 	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)  in dw_mipi_dsi_video_mode_config()
888 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_dsi_video_mode_config()
890 	if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)  in dw_mipi_dsi_video_mode_config()
891 		dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_video_mode_config()
895 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_enable()  argument
897 	const struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_enable()
899 	dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_enable()
902 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_enable()
904 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {  in dw_mipi_dsi_enable()
905 		dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE);  in dw_mipi_dsi_enable()
907 		dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel));  in dw_mipi_dsi_enable()
908 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);  in dw_mipi_dsi_enable()
909 		dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay);  in dw_mipi_dsi_enable()
910 		dsi_update_bits(dsi, DSI_MODE_CFG,  in dw_mipi_dsi_enable()
914 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_enable()
916 	if (dsi->slave)  in dw_mipi_dsi_enable()
917 		dw_mipi_dsi_enable(dsi->slave);  in dw_mipi_dsi_enable()
920 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_disable()  argument
922 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_disable()
923 	dsi_write(dsi, DSI_LPCLK_CTRL, 0);  in dw_mipi_dsi_disable()
924 	dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0);  in dw_mipi_dsi_disable()
925 	dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE);  in dw_mipi_dsi_disable()
926 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_disable()
928 	if (dsi->slave)  in dw_mipi_dsi_disable()
929 		dw_mipi_dsi_disable(dsi->slave);  in dw_mipi_dsi_disable()
932 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_post_disable()  argument
934 	if (!dsi->prepared)  in dw_mipi_dsi_post_disable()
937 	if (dsi->master)  in dw_mipi_dsi_post_disable()
938 		dw_mipi_dsi_post_disable(dsi->master);  in dw_mipi_dsi_post_disable()
940 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_post_disable()
941 	dsi_write(dsi, DSI_PHY_RSTZ, 0);  in dw_mipi_dsi_post_disable()
943 	if (dsi->dphy.phy)  in dw_mipi_dsi_post_disable()
944 		rockchip_phy_power_off(dsi->dphy.phy);  in dw_mipi_dsi_post_disable()
946 	dsi->prepared = false;  in dw_mipi_dsi_post_disable()
948 	if (dsi->slave)  in dw_mipi_dsi_post_disable()
949 		dw_mipi_dsi_post_disable(dsi->slave);  in dw_mipi_dsi_post_disable()
952 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_init()  argument
956 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_init()
959 	esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);  in dw_mipi_dsi_init()
960 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |  in dw_mipi_dsi_init()
964 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_dpi_config()  argument
969 	switch (dsi->format) {  in dw_mipi_dsi_dpi_config()
989 	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));  in dw_mipi_dsi_dpi_config()
990 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);  in dw_mipi_dsi_dpi_config()
991 	dsi_write(dsi, DSI_DPI_CFG_POL, val);  in dw_mipi_dsi_dpi_config()
992 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)  in dw_mipi_dsi_dpi_config()
996 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_packet_handler_config()  argument
1000 	if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)  in dw_mipi_dsi_packet_handler_config()
1003 	dsi_write(dsi, DSI_PCKHDL_CFG, val);  in dw_mipi_dsi_packet_handler_config()
1006 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_video_packet_config()  argument
1009 	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));  in dw_mipi_dsi_video_packet_config()
1012 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_command_mode_config()  argument
1014 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));  in dw_mipi_dsi_command_mode_config()
1015 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);  in dw_mipi_dsi_command_mode_config()
1019 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_get_hcomponent_lbcc()  argument
1024 	lbcc = hcomponent * dsi->lane_mbps * 1000 / 8;  in dw_mipi_dsi_get_hcomponent_lbcc()
1026 	if (!dsi->mode.clock)  in dw_mipi_dsi_get_hcomponent_lbcc()
1029 	return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock);  in dw_mipi_dsi_get_hcomponent_lbcc()
1032 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_line_timer_config()  argument
1035 	struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_line_timer_config()
1041 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);  in dw_mipi_dsi_line_timer_config()
1042 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1044 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);  in dw_mipi_dsi_line_timer_config()
1045 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1047 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);  in dw_mipi_dsi_line_timer_config()
1048 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1051 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_vertical_timing_config()  argument
1054 	struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_vertical_timing_config()
1061 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);  in dw_mipi_dsi_vertical_timing_config()
1062 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);  in dw_mipi_dsi_vertical_timing_config()
1063 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);  in dw_mipi_dsi_vertical_timing_config()
1064 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);  in dw_mipi_dsi_vertical_timing_config()
1067 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_dphy_timing_config()  argument
1069 	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)  in dw_mipi_dsi_dphy_timing_config()
1072 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)  in dw_mipi_dsi_dphy_timing_config()
1076 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_dphy_interface_config()  argument
1078 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |  in dw_mipi_dsi_dphy_interface_config()
1079 		  N_LANES(dsi->lanes));  in dw_mipi_dsi_dphy_interface_config()
1082 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_clear_err()  argument
1084 	dsi_read(dsi, DSI_INT_ST0);  in dw_mipi_dsi_clear_err()
1085 	dsi_read(dsi, DSI_INT_ST1);  in dw_mipi_dsi_clear_err()
1086 	dsi_write(dsi, DSI_INT_MSK0, 0);  in dw_mipi_dsi_clear_err()
1087 	dsi_write(dsi, DSI_INT_MSK1, 0);  in dw_mipi_dsi_clear_err()
1093 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_init()  local
1095 	conn_state->disp_info  = rockchip_get_disp_info(conn_state->type, dsi->id);  in dw_mipi_dsi_connector_init()
1096 	dsi->dphy.phy = conn->phy;  in dw_mipi_dsi_connector_init()
1101 		dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;  in dw_mipi_dsi_connector_init()
1104 	if (dsi->id) {  in dw_mipi_dsi_connector_init()
1108 		ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000",  in dw_mipi_dsi_connector_init()
1113 		dsi->master = dev_get_priv(dev);  in dw_mipi_dsi_connector_init()
1114 		if (!dsi->master)  in dw_mipi_dsi_connector_init()
1121 	if (dsi->lanes > 4) {  in dw_mipi_dsi_connector_init()
1127 						"dsi@ff964000",  in dw_mipi_dsi_connector_init()
1129 						"dsi@ff968000",  in dw_mipi_dsi_connector_init()
1131 						"dsi@fe070000",  in dw_mipi_dsi_connector_init()
1137 		dsi->slave = dev_get_priv(dev);  in dw_mipi_dsi_connector_init()
1138 		if (!dsi->slave)  in dw_mipi_dsi_connector_init()
1141 		dsi->lanes /= 2;  in dw_mipi_dsi_connector_init()
1142 		dsi->slave->lanes = dsi->lanes;  in dw_mipi_dsi_connector_init()
1143 		dsi->slave->format = dsi->format;  in dw_mipi_dsi_connector_init()
1144 		dsi->slave->mode_flags = dsi->mode_flags;  in dw_mipi_dsi_connector_init()
1145 		dsi->slave->channel = dsi->channel;  in dw_mipi_dsi_connector_init()
1148 		if (dsi->data_swap)  in dw_mipi_dsi_connector_init()
1166 		dsi->slave->dphy.phy = phy;  in dw_mipi_dsi_connector_init()
1176 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate)  in dw_mipi_dsi_set_hs_clk()  argument
1178 	rate = rockchip_phy_set_pll(dsi->dphy.phy, rate);  in dw_mipi_dsi_set_hs_clk()
1179 	dsi->lane_mbps = rate / 1000 / 1000;  in dw_mipi_dsi_set_hs_clk()
1182 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_host_init()  argument
1184 	dw_mipi_dsi_init(dsi);  in dw_mipi_dsi_host_init()
1185 	dw_mipi_dsi_dpi_config(dsi, &dsi->mode);  in dw_mipi_dsi_host_init()
1186 	dw_mipi_dsi_packet_handler_config(dsi);  in dw_mipi_dsi_host_init()
1187 	dw_mipi_dsi_video_mode_config(dsi);  in dw_mipi_dsi_host_init()
1188 	dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);  in dw_mipi_dsi_host_init()
1189 	dw_mipi_dsi_command_mode_config(dsi);  in dw_mipi_dsi_host_init()
1190 	dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE);  in dw_mipi_dsi_host_init()
1191 	dw_mipi_dsi_line_timer_config(dsi);  in dw_mipi_dsi_host_init()
1192 	dw_mipi_dsi_vertical_timing_config(dsi);  in dw_mipi_dsi_host_init()
1193 	dw_mipi_dsi_dphy_timing_config(dsi);  in dw_mipi_dsi_host_init()
1194 	dw_mipi_dsi_dphy_interface_config(dsi);  in dw_mipi_dsi_host_init()
1195 	dw_mipi_dsi_clear_err(dsi);  in dw_mipi_dsi_host_init()
1198 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id)  in dw_mipi_dsi_vop_routing()  argument
1200 	grf_field_write(dsi, VOPSEL, vop_id);  in dw_mipi_dsi_vop_routing()
1202 	if (dsi->slave)  in dw_mipi_dsi_vop_routing()
1203 		grf_field_write(dsi->slave, VOPSEL, vop_id);  in dw_mipi_dsi_vop_routing()
1206 static void mipi_dphy_init(struct dw_mipi_dsi *dsi)  in mipi_dphy_init()  argument
1210 	mipi_dphy_enableclk_deassert(dsi);  in mipi_dphy_init()
1211 	mipi_dphy_shutdownz_assert(dsi);  in mipi_dphy_init()
1212 	mipi_dphy_rstz_assert(dsi);  in mipi_dphy_init()
1213 	testif_testclr_assert(dsi);  in mipi_dphy_init()
1216 	grf_field_write(dsi, MASTERSLAVEZ, 1);  in mipi_dphy_init()
1219 	grf_field_write(dsi, BASEDIR, 0);  in mipi_dphy_init()
1222 	grf_field_write(dsi, TURNREQUEST, 0);  in mipi_dphy_init()
1223 	grf_field_write(dsi, TURNDISABLE, 0);  in mipi_dphy_init()
1224 	grf_field_write(dsi, FORCETXSTOPMODE, 0);  in mipi_dphy_init()
1225 	grf_field_write(dsi, FORCERXMODE, 0);  in mipi_dphy_init()
1228 	testif_testclr_deassert(dsi);  in mipi_dphy_init()
1230 	if (!dsi->dphy.phy)  in mipi_dphy_init()
1231 		dw_mipi_dsi_phy_init(dsi);  in mipi_dphy_init()
1234 	grf_field_write(dsi, ENABLE_N, map[dsi->lanes]);  in mipi_dphy_init()
1237 	grf_field_write(dsi, ENABLECLK, 1);  in mipi_dphy_init()
1239 	mipi_dphy_enableclk_assert(dsi);  in mipi_dphy_init()
1242 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_pre_enable()  argument
1244 	if (dsi->prepared)  in dw_mipi_dsi_pre_enable()
1247 	if (dsi->master)  in dw_mipi_dsi_pre_enable()
1248 		dw_mipi_dsi_pre_enable(dsi->master);  in dw_mipi_dsi_pre_enable()
1250 	dw_mipi_dsi_host_init(dsi);  in dw_mipi_dsi_pre_enable()
1251 	mipi_dphy_init(dsi);  in dw_mipi_dsi_pre_enable()
1252 	mipi_dphy_power_on(dsi);  in dw_mipi_dsi_pre_enable()
1253 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_pre_enable()
1255 	dsi->prepared = true;  in dw_mipi_dsi_pre_enable()
1257 	if (dsi->slave)  in dw_mipi_dsi_pre_enable()
1258 		dw_mipi_dsi_pre_enable(dsi->slave);  in dw_mipi_dsi_pre_enable()
1266 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_prepare()  local
1269 	memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode));  in dw_mipi_dsi_connector_prepare()
1270 	if (dsi->slave) {  in dw_mipi_dsi_connector_prepare()
1271 		dsi->mode.hdisplay /= 2;  in dw_mipi_dsi_connector_prepare()
1272 		memcpy(&dsi->slave->mode, &dsi->mode,  in dw_mipi_dsi_connector_prepare()
1276 	lane_rate = dw_mipi_dsi_get_lane_rate(dsi);  in dw_mipi_dsi_connector_prepare()
1277 	if (dsi->dphy.phy)  in dw_mipi_dsi_connector_prepare()
1278 		dw_mipi_dsi_set_hs_clk(dsi, lane_rate);  in dw_mipi_dsi_connector_prepare()
1280 		dw_mipi_dsi_set_pll(dsi, lane_rate);  in dw_mipi_dsi_connector_prepare()
1282 	if (dsi->slave && dsi->slave->dphy.phy)  in dw_mipi_dsi_connector_prepare()
1283 		dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate);  in dw_mipi_dsi_connector_prepare()
1285 	printf("final DSI-Link bandwidth: %u Mbps x %d\n",  in dw_mipi_dsi_connector_prepare()
1286 	       dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);  in dw_mipi_dsi_connector_prepare()
1288 	dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id);  in dw_mipi_dsi_connector_prepare()
1289 	dw_mipi_dsi_pre_enable(dsi);  in dw_mipi_dsi_connector_prepare()
1297 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_unprepare()  local
1299 	dw_mipi_dsi_post_disable(dsi);  in dw_mipi_dsi_connector_unprepare()
1305 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_enable()  local
1307 	dw_mipi_dsi_enable(dsi);  in dw_mipi_dsi_connector_enable()
1315 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_disable()  local
1317 	dw_mipi_dsi_disable(dsi);  in dw_mipi_dsi_connector_disable()
1332 	struct dw_mipi_dsi *dsi = dev_get_priv(dev);  in dw_mipi_dsi_probe()  local
1337 	dsi->base = dev_read_addr_ptr(dev);  in dw_mipi_dsi_probe()
1338 	dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);  in dw_mipi_dsi_probe()
1339 	if (IS_ERR(dsi->grf))  in dw_mipi_dsi_probe()
1340 		return PTR_ERR(dsi->grf);  in dw_mipi_dsi_probe()
1342 	id = of_alias_get_id(ofnode_to_np(dev->node), "dsi");  in dw_mipi_dsi_probe()
1346 	dsi->dev = dev;  in dw_mipi_dsi_probe()
1347 	dsi->pdata = pdata;  in dw_mipi_dsi_probe()
1348 	dsi->id = id;  in dw_mipi_dsi_probe()
1349 	dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap");  in dw_mipi_dsi_probe()
1351 	rockchip_connector_bind(&dsi->connector, dev, dsi->id, &dw_mipi_dsi_connector_funcs, NULL,  in dw_mipi_dsi_probe()
1563 		.compatible = "rockchip,px30-mipi-dsi",
1567 		.compatible = "rockchip,rk1808-mipi-dsi",
1571 		.compatible = "rockchip,rk3128-mipi-dsi",
1575 		.compatible = "rockchip,rk3288-mipi-dsi",
1579 		.compatible = "rockchip,rk3366-mipi-dsi",
1583 		.compatible = "rockchip,rk3368-mipi-dsi",
1587 		.compatible = "rockchip,rk3399-mipi-dsi",
1591 		.compatible = "rockchip,rk3562-mipi-dsi",
1595 		.compatible = "rockchip,rk3568-mipi-dsi",
1599 		.compatible = "rockchip,rv1108-mipi-dsi",
1603 		.compatible = "rockchip,rv1126-mipi-dsi",
1612 	struct dw_mipi_dsi *dsi = dev_get_priv(host->dev);  in dw_mipi_dsi_host_transfer()  local
1614 	return dw_mipi_dsi_transfer(dsi, msg);  in dw_mipi_dsi_host_transfer()
1620 	struct dw_mipi_dsi *dsi = dev_get_priv(host->dev);  in dw_mipi_dsi_host_attach()  local
1625 	dsi->lanes = device->lanes;  in dw_mipi_dsi_host_attach()
1626 	dsi->channel = device->channel;  in dw_mipi_dsi_host_attach()
1627 	dsi->format = device->format;  in dw_mipi_dsi_host_attach()
1628 	dsi->mode_flags = device->mode_flags;  in dw_mipi_dsi_host_attach()
1659 	device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);  in dw_mipi_dsi_child_post_bind()
1660 	device->format = dev_read_u32_default(dev, "dsi,format",  in dw_mipi_dsi_child_post_bind()
1662 	device->mode_flags = dev_read_u32_default(dev, "dsi,flags",  in dw_mipi_dsi_child_post_bind()