780 	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;  in hdmi_phy_configure_dwc_hdmi_3d_tx()  local
798 	for (; phy_config->mpixelclock != ~0UL; phy_config++)  in hdmi_phy_configure_dwc_hdmi_3d_tx()
799 		if (tmdsclock <= phy_config->mpixelclock)  in hdmi_phy_configure_dwc_hdmi_3d_tx()
804 	    phy_config->mpixelclock == ~0UL)  in hdmi_phy_configure_dwc_hdmi_3d_tx()
826 	dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);  in hdmi_phy_configure_dwc_hdmi_3d_tx()
827 	dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,  in hdmi_phy_configure_dwc_hdmi_3d_tx()
829 	dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,  in hdmi_phy_configure_dwc_hdmi_3d_tx()
2384 	if (ret > 0 && hdmi->plat_data->phy_config) {  in rockchip_dw_hdmi_init()
2385 		u32 phy_config[ret / 4];  in rockchip_dw_hdmi_init()  local
2388 		dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4);  in rockchip_dw_hdmi_init()
2391 			if (phy_config[i * 4] != 0)  in rockchip_dw_hdmi_init()
2392 				hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4];  in rockchip_dw_hdmi_init()
2394 				hdmi->plat_data->phy_config[i].mpixelclock = ~0UL;  in rockchip_dw_hdmi_init()
2395 			hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1];  in rockchip_dw_hdmi_init()
2396 			hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2];  in rockchip_dw_hdmi_init()
2397 			hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3];  in rockchip_dw_hdmi_init()