324 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size)  in dw_dp_aux_write_data()  argument
335 		regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value);  in dw_dp_aux_write_data()
341 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size)  in dw_dp_aux_read_data()  argument
349 		regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value);  in dw_dp_aux_read_data()
364 	struct dw_dp *dp = dev_get_priv(aux->dev);  in dw_dp_aux_transfer()  local
373 		ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size);  in dw_dp_aux_transfer()
391 	regmap_write(dp->regmap, DPTX_AUX_CMD, value);  in dw_dp_aux_transfer()
393 	timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT,  in dw_dp_aux_transfer()
401 	regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT);  in dw_dp_aux_transfer()
403 	regmap_read(dp->regmap, DPTX_AUX_STATUS, &value);  in dw_dp_aux_transfer()
420 			ret = dw_dp_aux_read_data(dp, msg->buffer, count);  in dw_dp_aux_transfer()
429 static bool dw_dp_bandwidth_ok(struct dw_dp *dp,  in dw_dp_bandwidth_ok()  argument
443 static void dw_dp_hpd_init(struct dw_dp *dp)  in dw_dp_hpd_init()  argument
445 	if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) {  in dw_dp_hpd_init()
446 		regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD,  in dw_dp_hpd_init()
452 	regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE,  in dw_dp_hpd_init()
459 	regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,  in dw_dp_hpd_init()
463 static void dw_dp_aux_init(struct dw_dp *dp)  in dw_dp_aux_init()  argument
465 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET,  in dw_dp_aux_init()
468 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET,  in dw_dp_aux_init()
471 	regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,  in dw_dp_aux_init()
476 static void dw_dp_init(struct dw_dp *dp)  in dw_dp_init()  argument
478 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET,  in dw_dp_init()
481 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET,  in dw_dp_init()
484 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET,  in dw_dp_init()
487 	regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET,  in dw_dp_init()
490 	regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN,  in dw_dp_init()
493 	dw_dp_hpd_init(dp);  in dw_dp_init()
494 	dw_dp_aux_init(dp);  in dw_dp_init()
497 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern)  in dw_dp_phy_set_pattern()  argument
499 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL,  in dw_dp_phy_set_pattern()
503 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes)  in dw_dp_phy_xmit_enable()  argument
519 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE,  in dw_dp_phy_xmit_enable()
523 static int dw_dp_link_power_up(struct dw_dp *dp)  in dw_dp_link_power_up()  argument
525 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_power_up()
532 	ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);  in dw_dp_link_power_up()
539 	ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);  in dw_dp_link_power_up()
547 static int dw_dp_link_probe(struct dw_dp *dp)  in dw_dp_link_probe()  argument
549 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_probe()
553 	ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);  in dw_dp_link_probe()
557 	ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,  in dw_dp_link_probe()
566 	link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100),  in dw_dp_link_probe()
568 	link->lanes = min_t(u8, dp->phy.attrs.bus_width,  in dw_dp_link_probe()
581 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)  in dw_dp_link_train_update_vs_emph()  argument
583 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_train_update_vs_emph()
594 		phy_cfg.dp.voltage[i] = vs[i];  in dw_dp_link_train_update_vs_emph()
595 		phy_cfg.dp.pre[i] = pe[i];  in dw_dp_link_train_update_vs_emph()
597 	phy_cfg.dp.lanes = lanes;  in dw_dp_link_train_update_vs_emph()
598 	phy_cfg.dp.link_rate = link->rate / 100;  in dw_dp_link_train_update_vs_emph()
599 	phy_cfg.dp.set_lanes = false;  in dw_dp_link_train_update_vs_emph()
600 	phy_cfg.dp.set_rate = false;  in dw_dp_link_train_update_vs_emph()
601 	phy_cfg.dp.set_voltages = true;  in dw_dp_link_train_update_vs_emph()
602 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in dw_dp_link_train_update_vs_emph()
609 	ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);  in dw_dp_link_train_update_vs_emph()
616 static int dw_dp_link_configure(struct dw_dp *dp)  in dw_dp_link_configure()  argument
618 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_configure()
624 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,  in dw_dp_link_configure()
627 	phy_cfg.dp.lanes = link->lanes;  in dw_dp_link_configure()
628 	phy_cfg.dp.link_rate = link->rate / 100;  in dw_dp_link_configure()
629 	phy_cfg.dp.ssc = link->caps.ssc;  in dw_dp_link_configure()
630 	phy_cfg.dp.set_lanes = true;  in dw_dp_link_configure()
631 	phy_cfg.dp.set_rate = true;  in dw_dp_link_configure()
632 	phy_cfg.dp.set_voltages = false;  in dw_dp_link_configure()
633 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in dw_dp_link_configure()
637 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES,  in dw_dp_link_configure()
655 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE,  in dw_dp_link_configure()
659 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,  in dw_dp_link_configure()
662 	dw_dp_phy_xmit_enable(dp, link->lanes);  in dw_dp_link_configure()
669 		regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,  in dw_dp_link_configure()
672 		regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,  in dw_dp_link_configure()
676 	ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));  in dw_dp_link_configure()
683 	ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf,  in dw_dp_link_configure()
709 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern)  in dw_dp_link_train_set_pattern()  argument
717 		regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,  in dw_dp_link_train_set_pattern()
720 		regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,  in dw_dp_link_train_set_pattern()
726 		dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE);  in dw_dp_link_train_set_pattern()
729 		dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1);  in dw_dp_link_train_set_pattern()
732 		dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2);  in dw_dp_link_train_set_pattern()
735 		dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3);  in dw_dp_link_train_set_pattern()
738 		dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4);  in dw_dp_link_train_set_pattern()
744 	ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,  in dw_dp_link_train_set_pattern()
784 static int dw_dp_link_clock_recovery(struct dw_dp *dp)  in dw_dp_link_clock_recovery()  argument
786 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_clock_recovery()
791 	ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);  in dw_dp_link_clock_recovery()
796 		ret = dw_dp_link_train_update_vs_emph(dp);  in dw_dp_link_clock_recovery()
802 		ret = drm_dp_dpcd_read_link_status(&dp->aux, status);  in dw_dp_link_clock_recovery()
804 			dev_err(dp->dev, "failed to read link status: %d\n",  in dw_dp_link_clock_recovery()
831 static int dw_dp_link_channel_equalization(struct dw_dp *dp)  in dw_dp_link_channel_equalization()  argument
833 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_channel_equalization()
844 	ret = dw_dp_link_train_set_pattern(dp, pattern);  in dw_dp_link_channel_equalization()
849 		ret = dw_dp_link_train_update_vs_emph(dp);  in dw_dp_link_channel_equalization()
855 		ret = drm_dp_dpcd_read_link_status(&dp->aux, status);  in dw_dp_link_channel_equalization()
860 			dev_err(dp->dev,  in dw_dp_link_channel_equalization()
878 static int dw_dp_link_downgrade(struct dw_dp *dp)  in dw_dp_link_downgrade()  argument
880 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_downgrade()
881 	struct dw_dp_video *video = &dp->video;  in dw_dp_link_downgrade()
897 	if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes,  in dw_dp_link_downgrade()
904 static int dw_dp_link_train(struct dw_dp *dp)  in dw_dp_link_train()  argument
906 	struct dw_dp_link *link = &dp->link;  in dw_dp_link_train()
915 	ret = dw_dp_link_configure(dp);  in dw_dp_link_train()
917 		dev_err(dp->dev, "failed to configure DP link: %d\n", ret);  in dw_dp_link_train()
921 	ret = dw_dp_link_clock_recovery(dp);  in dw_dp_link_train()
923 		dev_err(dp->dev, "clock recovery failed: %d\n", ret);  in dw_dp_link_train()
928 		dev_err(dp->dev, "clock recovery failed, downgrading link\n");  in dw_dp_link_train()
930 		ret = dw_dp_link_downgrade(dp);  in dw_dp_link_train()
939 	ret = dw_dp_link_channel_equalization(dp);  in dw_dp_link_train()
941 		dev_err(dp->dev, "channel equalization failed: %d\n", ret);  in dw_dp_link_train()
946 		dev_err(dp->dev,  in dw_dp_link_train()
949 		ret = dw_dp_link_downgrade(dp);  in dw_dp_link_train()
959 	dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);  in dw_dp_link_train()
963 static int dw_dp_link_enable(struct dw_dp *dp)  in dw_dp_link_enable()  argument
967 	ret = dw_dp_link_power_up(dp);  in dw_dp_link_enable()
971 	ret = dw_dp_link_train(dp);  in dw_dp_link_enable()
973 		dev_err(dp->dev, "link training failed: %d\n", ret);  in dw_dp_link_enable()
980 static int dw_dp_set_phy_default_config(struct dw_dp *dp)  in dw_dp_set_phy_default_config()  argument
982 	struct dw_dp_link *link = &dp->link;  in dw_dp_set_phy_default_config()
988 	link->lanes = dp->phy.attrs.bus_width;  in dw_dp_set_phy_default_config()
995 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,  in dw_dp_set_phy_default_config()
999 		phy_cfg.dp.voltage[i] = 3;  in dw_dp_set_phy_default_config()
1000 		phy_cfg.dp.pre[i] = 0;  in dw_dp_set_phy_default_config()
1002 	phy_cfg.dp.lanes = link->lanes;  in dw_dp_set_phy_default_config()
1003 	phy_cfg.dp.link_rate = link->rate / 100;  in dw_dp_set_phy_default_config()
1004 	phy_cfg.dp.ssc = link->caps.ssc;  in dw_dp_set_phy_default_config()
1005 	phy_cfg.dp.set_lanes = true;  in dw_dp_set_phy_default_config()
1006 	phy_cfg.dp.set_rate = true;  in dw_dp_set_phy_default_config()
1007 	phy_cfg.dp.set_voltages = true;  in dw_dp_set_phy_default_config()
1008 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in dw_dp_set_phy_default_config()
1012 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES,  in dw_dp_set_phy_default_config()
1030 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE,  in dw_dp_set_phy_default_config()
1034 	regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,  in dw_dp_set_phy_default_config()
1037 	dw_dp_phy_xmit_enable(dp, link->lanes);  in dw_dp_set_phy_default_config()
1039 	regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,  in dw_dp_set_phy_default_config()
1042 	dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE);  in dw_dp_set_phy_default_config()
1046 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp)  in dw_dp_send_sdp()  argument
1055 	regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header));  in dw_dp_send_sdp()
1059 		regmap_write(dp->regmap, reg + i * 4,  in dw_dp_send_sdp()
1063 		regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,  in dw_dp_send_sdp()
1068 		regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL,  in dw_dp_send_sdp()
1112 static int dw_dp_send_vsc_sdp(struct dw_dp *dp)  in dw_dp_send_vsc_sdp()  argument
1114 	struct dw_dp_video *video = &dp->video;  in dw_dp_send_vsc_sdp()
1148 	return dw_dp_send_sdp(dp, &sdp);  in dw_dp_send_vsc_sdp()
1151 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode)  in dw_dp_video_set_pixel_mode()  argument
1162 	regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT,  in dw_dp_video_set_pixel_mode()
1168 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc,  in dw_dp_video_set_msa()  argument
1171 	struct dw_dp_link *link = &dp->link;  in dw_dp_video_set_msa()
1213 	regmap_write(dp->regmap, DPTX_VIDEO_MSA1,  in dw_dp_video_set_msa()
1215 	regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc));  in dw_dp_video_set_msa()
1216 	regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8));  in dw_dp_video_set_msa()
1221 static int dw_dp_video_enable(struct dw_dp *dp)  in dw_dp_video_enable()  argument
1223 	struct dw_dp_video *video = &dp->video;  in dw_dp_video_enable()
1224 	struct dw_dp_link *link = &dp->link;  in dw_dp_video_enable()
1240 	ret = dw_dp_video_set_pixel_mode(dp, pixel_mode);  in dw_dp_video_enable()
1244 	ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart);  in dw_dp_video_enable()
1248 	regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING,  in dw_dp_video_enable()
1257 	regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value);  in dw_dp_video_enable()
1274 	regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value);  in dw_dp_video_enable()
1279 	regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2,  in dw_dp_video_enable()
1285 	regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3,  in dw_dp_video_enable()
1292 	regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4,  in dw_dp_video_enable()
1371 	regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5,  in dw_dp_video_enable()
1380 	regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL,  in dw_dp_video_enable()
1385 	regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,  in dw_dp_video_enable()
1389 		dw_dp_send_vsc_sdp(dp);  in dw_dp_video_enable()
1394 static bool dw_dp_detect(struct dw_dp *dp)  in dw_dp_detect()  argument
1398 	if (dm_gpio_is_valid(&dp->hpd_gpio))  in dw_dp_detect()
1399 		return dm_gpio_get_value(&dp->hpd_gpio);  in dw_dp_detect()
1401 	regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);  in dw_dp_detect()
1403 		regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG);  in dw_dp_detect()
1413 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_init()  local
1416 	conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;  in dw_dp_connector_init()
1420 	clk_set_defaults(dp->dev);  in dw_dp_connector_init()
1422 	reset_assert(&dp->reset);  in dw_dp_connector_init()
1424 	reset_deassert(&dp->reset);  in dw_dp_connector_init()
1427 							dp->id);  in dw_dp_connector_init()
1428 	dw_dp_init(dp);  in dw_dp_connector_init()
1429 	ret = generic_phy_power_on(&dp->phy);  in dw_dp_connector_init()
1438 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_get_edid()  local
1440 	ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid);  in dw_dp_connector_get_edid()
1465 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_prepare()  local
1466 	struct dw_dp_video *video = &dp->video;  in dw_dp_connector_prepare()
1483 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_enable()  local
1484 	struct dw_dp_video *video = &dp->video;  in dw_dp_connector_enable()
1490 	if (dp->force_output) {  in dw_dp_connector_enable()
1491 		ret = dw_dp_set_phy_default_config(dp);  in dw_dp_connector_enable()
1495 		ret = dw_dp_link_enable(dp);  in dw_dp_connector_enable()
1502 	ret = dw_dp_video_enable(dp);  in dw_dp_connector_enable()
1520 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_detect()  local
1524 		status = dw_dp_detect(dp);  in dw_dp_connector_detect()
1531 		dp->force_output = true;  in dw_dp_connector_detect()
1533 	if (!status && !dp->force_output)  in dw_dp_connector_detect()
1534 		generic_phy_power_off(&dp->phy);  in dw_dp_connector_detect()
1536 	if (status && !dp->force_output) {  in dw_dp_connector_detect()
1537 		ret = dw_dp_link_probe(dp);  in dw_dp_connector_detect()
1539 			printf("failed to probe DP link: %d\n", ret);  in dw_dp_connector_detect()
1545 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data)  in dw_dp_mode_valid()  argument
1547 	struct dw_dp_link *link = &dp->link;  in dw_dp_mode_valid()
1563 		if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes,  in dw_dp_mode_valid()
1571 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data)  in dw_dp_get_output_bus_fmts()  argument
1573 	struct dw_dp_link *link = &dp->link;  in dw_dp_get_output_bus_fmts()
1593 		if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes,  in dw_dp_get_output_bus_fmts()
1610 	struct dw_dp *dp = dev_get_priv(conn->dev);  in dw_dp_connector_get_timing()  local
1625 	if (!dp->force_output) {  in dw_dp_connector_get_timing()
1626 		ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid);  in dw_dp_connector_get_timing()
1645 		dw_dp_mode_valid(dp, &edid_data);  in dw_dp_connector_get_timing()
1664 		bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data);  in dw_dp_connector_get_timing()
1698 static int dw_dp_ddc_init(struct dw_dp *dp)  in dw_dp_ddc_init()  argument
1700 	dp->aux.name = "dw-dp";  in dw_dp_ddc_init()
1701 	dp->aux.dev = dp->dev;  in dw_dp_ddc_init()
1702 	dp->aux.transfer = dw_dp_aux_transfer;  in dw_dp_ddc_init()
1703 	dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer;  in dw_dp_ddc_init()
1708 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp)  in dw_dp_parse_link_frequencies()  argument
1710 	struct udevice *dev = dp->dev;  in dw_dp_parse_link_frequencies()
1740 static int dw_dp_parse_dt(struct dw_dp *dp)  in dw_dp_parse_dt()  argument
1742 	dp->force_hpd = dev_read_bool(dp->dev, "force-hpd");  in dw_dp_parse_dt()
1744 	dp->max_link_rate = dw_dp_parse_link_frequencies(dp);  in dw_dp_parse_dt()
1745 	if (!dp->max_link_rate)  in dw_dp_parse_dt()
1746 		dp->max_link_rate = 810000;  in dw_dp_parse_dt()
1753 	struct dw_dp *dp = dev_get_priv(dev);  in dw_dp_probe()  local
1756 	ret = regmap_init_mem(dev, &dp->regmap);  in dw_dp_probe()
1760 	dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp");  in dw_dp_probe()
1761 	if (dp->id < 0)  in dw_dp_probe()
1762 		dp->id = 0;  in dw_dp_probe()
1764 	ret = reset_get_by_index(dev, 0, &dp->reset);  in dw_dp_probe()
1770 	ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio,  in dw_dp_probe()
1777 	generic_phy_get_by_index(dev, 0, &dp->phy);  in dw_dp_probe()
1779 	dp->dev = dev;  in dw_dp_probe()
1781 	ret = dw_dp_parse_dt(dp);  in dw_dp_probe()
1787 	dw_dp_ddc_init(dp);  in dw_dp_probe()
1789 	rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL,  in dw_dp_probe()
1797 		.compatible = "rockchip,rk3588-dp",