Lines Matching +full:0 +full:x7a0
18 #define ANALOGIX_DP_TX_SW_RESET 0x14
19 #define ANALOGIX_DP_FUNC_EN_1 0x18
20 #define ANALOGIX_DP_FUNC_EN_2 0x1C
21 #define ANALOGIX_DP_VIDEO_CTL_1 0x20
22 #define ANALOGIX_DP_VIDEO_CTL_2 0x24
23 #define ANALOGIX_DP_VIDEO_CTL_3 0x28
24 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C
25 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
26 #define ANALOGIX_DP_VIDEO_CTL_10 0x44
28 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48
29 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C
30 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50
31 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54
32 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58
33 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C
34 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60
35 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64
36 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68
37 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C
38 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70
39 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74
40 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78
41 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C
42 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80
43 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84
44 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88
46 #define ANALOGIX_DP_PLL_REG_1 0xfc
47 #define ANALOGIX_DP_PLL_REG_2 0x9e4
48 #define ANALOGIX_DP_PLL_REG_3 0x9e8
49 #define ANALOGIX_DP_PLL_REG_4 0x9ec
50 #define ANALOGIX_DP_PLL_REG_5 0xa00
52 #define ANALOGIX_DP_BIAS 0x124
53 #define ANALOGIX_DP_PD 0x12c
55 #define ANALOGIX_DP_LANE_MAP 0x35C
57 #define ANALOGIX_DP_ANALOG_CTL_1 0x370
58 #define ANALOGIX_DP_ANALOG_CTL_2 0x374
59 #define ANALOGIX_DP_ANALOG_CTL_3 0x378
60 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C
61 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380
63 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390
65 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4
66 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8
67 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC
68 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0
69 #define ANALOGIX_DP_INT_STA 0x3DC
70 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0
71 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4
72 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8
73 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC
74 #define ANALOGIX_DP_INT_STA_MASK 0x3F8
75 #define ANALOGIX_DP_INT_CTL 0x3FC
77 #define ANALOGIX_DP_SYS_CTL_1 0x600
78 #define ANALOGIX_DP_SYS_CTL_2 0x604
79 #define ANALOGIX_DP_SYS_CTL_3 0x608
80 #define ANALOGIX_DP_SYS_CTL_4 0x60C
82 #define ANALOGIX_DP_PKT_SEND_CTL 0x640
83 #define ANALOGIX_DP_HDCP_CTL 0x648
85 #define ANALOGIX_DP_LINK_BW_SET 0x680
86 #define ANALOGIX_DP_LANE_COUNT_SET 0x684
87 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688
88 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C
89 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690
90 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694
91 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698
93 #define ANALOGIX_DP_DEBUG_CTL 0x6C0
94 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4
95 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8
96 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0
98 #define ANALOGIX_DP_M_VID_0 0x700
99 #define ANALOGIX_DP_M_VID_1 0x704
100 #define ANALOGIX_DP_M_VID_2 0x708
101 #define ANALOGIX_DP_N_VID_0 0x70C
102 #define ANALOGIX_DP_N_VID_1 0x710
103 #define ANALOGIX_DP_N_VID_2 0x714
105 #define ANALOGIX_DP_PLL_CTL 0x71C
106 #define ANALOGIX_DP_PHY_PD 0x720
107 #define ANALOGIX_DP_PHY_TEST 0x724
109 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730
110 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C
112 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764
113 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778
114 #define ANALOGIX_DP_AUX_CH_STA 0x780
115 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788
116 #define ANALOGIX_DP_AUX_RX_COMM 0x78C
117 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790
118 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794
119 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798
120 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C
121 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0
122 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4
124 #define ANALOGIX_DP_BUF_DATA_0 0x7C0
126 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800
129 #define RESET_DP_TX (0x1 << 0)
132 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
133 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
134 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
135 #define AUD_FUNC_EN_N (0x1 << 3)
136 #define HDCP_FUNC_EN_N (0x1 << 2)
137 #define CRC_FUNC_EN_N (0x1 << 1)
138 #define SW_FUNC_EN_N (0x1 << 0)
141 #define SSC_FUNC_EN_N (0x1 << 7)
142 #define AUX_FUNC_EN_N (0x1 << 2)
143 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
144 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
147 #define VIDEO_EN (0x1 << 7)
148 #define HDCP_VIDEO_MUTE (0x1 << 6)
151 #define BIST_EN (0x1 << 3)
152 #define BIST_WIDTH(x) (((x) & 0x1) << 2)
153 #define BIST_TYPE(x) (((x) & 0x3) << 0)
156 #define IN_D_RANGE_MASK (0x1 << 7)
158 #define IN_D_RANGE_CEA (0x1 << 7)
159 #define IN_D_RANGE_VESA (0x0 << 7)
160 #define IN_BPC_MASK (0x7 << 4)
162 #define IN_BPC_12_BITS (0x3 << 4)
163 #define IN_BPC_10_BITS (0x2 << 4)
164 #define IN_BPC_8_BITS (0x1 << 4)
165 #define IN_BPC_6_BITS (0x0 << 4)
166 #define IN_COLOR_F_MASK (0x3 << 0)
167 #define IN_COLOR_F_SHIFT (0)
168 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
169 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
170 #define IN_COLOR_F_RGB (0x0 << 0)
173 #define IN_YC_COEFFI_MASK (0x1 << 7)
175 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
176 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
177 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
179 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
180 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
183 #define VID_HRES_TH(x) (((x) & 0xf) << 4)
184 #define VID_VRES_TH(x) (((x) & 0xf) << 0)
187 #define FORMAT_SEL (0x1 << 4)
188 #define INTERACE_SCAN_CFG (0x1 << 2)
189 #define VSYNC_POLARITY_CFG (0x1 << 1)
190 #define HSYNC_POLARITY_CFG (0x1 << 0)
193 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0)
196 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0)
199 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0)
202 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0)
205 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0)
208 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0)
211 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0)
214 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0)
217 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0)
220 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0)
223 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0)
226 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0)
229 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0)
232 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0)
235 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0)
238 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0)
241 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0)
244 #define REF_CLK_24M (0x1 << 0)
245 #define REF_CLK_27M (0x0 << 0)
246 #define REF_CLK_MASK (0x1 << 0)
249 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
250 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
251 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
252 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
253 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
254 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
255 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
256 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
257 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
258 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
259 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
260 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
261 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
262 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
263 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
264 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
267 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
270 #define SEL_24M (0x1 << 3)
271 #define TX_DVDD_BIT_1_0625V (0x4 << 0)
274 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
275 #define VCO_BIT_600_MICRO (0x5 << 0)
278 #define PD_RING_OSC (0x1 << 6)
279 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
280 #define TX_CUR1_2X (0x1 << 2)
281 #define TX_CUR_16_MA (0x3 << 0)
284 #define CH3_AMP_400_MV (0x0 << 24)
285 #define CH2_AMP_400_MV (0x0 << 16)
286 #define CH1_AMP_400_MV (0x0 << 8)
287 #define CH0_AMP_400_MV (0x0 << 0)
290 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
291 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
292 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
293 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
294 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
295 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
296 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
299 #define VSYNC_DET (0x1 << 7)
300 #define PLL_LOCK_CHG (0x1 << 6)
301 #define SPDIF_ERR (0x1 << 5)
302 #define SPDIF_UNSTBL (0x1 << 4)
303 #define VID_FORMAT_CHG (0x1 << 3)
304 #define AUD_CLK_CHG (0x1 << 2)
305 #define VID_CLK_CHG (0x1 << 1)
306 #define SW_INT (0x1 << 0)
309 #define ENC_EN_CHG (0x1 << 6)
310 #define HW_BKSV_RDY (0x1 << 3)
311 #define HW_SHA_DONE (0x1 << 2)
312 #define HW_AUTH_STATE_CHG (0x1 << 1)
313 #define HW_AUTH_DONE (0x1 << 0)
316 #define AFIFO_UNDER (0x1 << 7)
317 #define AFIFO_OVER (0x1 << 6)
318 #define R0_CHK_FLAG (0x1 << 5)
321 #define PSR_ACTIVE (0x1 << 7)
322 #define PSR_INACTIVE (0x1 << 6)
323 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
324 #define HOTPLUG_CHG (0x1 << 2)
325 #define HPD_LOST (0x1 << 1)
326 #define PLUG (0x1 << 0)
329 #define INT_HPD (0x1 << 6)
330 #define HW_TRAINING_FINISH (0x1 << 5)
331 #define RPLY_RECEIV (0x1 << 1)
332 #define AUX_ERR (0x1 << 0)
335 #define SOFT_INT_CTRL (0x1 << 2)
336 #define INT_POL1 (0x1 << 1)
337 #define INT_POL0 (0x1 << 0)
340 #define DET_STA (0x1 << 2)
341 #define FORCE_DET (0x1 << 1)
342 #define DET_CTRL (0x1 << 0)
345 #define CHA_CRI(x) (((x) & 0xf) << 4)
346 #define CHA_STA (0x1 << 2)
347 #define FORCE_CHA (0x1 << 1)
348 #define CHA_CTRL (0x1 << 0)
351 #define HPD_STATUS (0x1 << 6)
352 #define F_HPD (0x1 << 5)
353 #define HPD_CTRL (0x1 << 4)
354 #define HDCP_RDY (0x1 << 3)
355 #define STRM_VALID (0x1 << 2)
356 #define F_VALID (0x1 << 1)
357 #define VALID_CTRL (0x1 << 0)
360 #define FIX_M_AUD (0x1 << 4)
361 #define ENHANCED (0x1 << 3)
362 #define FIX_M_VID (0x1 << 2)
363 #define M_VID_UPDATE_CTRL (0x3 << 0)
366 #define SCRAMBLER_TYPE (0x1 << 9)
367 #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
368 #define SCRAMBLING_DISABLE (0x1 << 5)
369 #define SCRAMBLING_ENABLE (0x0 << 5)
370 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
371 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
372 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
373 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
374 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
375 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0)
376 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
377 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
378 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
381 #define PRE_EMPHASIS_SET_MASK (0x3 << 3)
385 #define PLL_LOCK (0x1 << 4)
386 #define F_PLL_LOCK (0x1 << 3)
387 #define PLL_LOCK_CTRL (0x1 << 2)
388 #define PN_INV (0x1 << 0)
391 #define DP_PLL_PD (0x1 << 7)
392 #define DP_PLL_RESET (0x1 << 6)
393 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
394 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
395 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
398 #define DP_PHY_PD (0x1 << 5)
399 #define AUX_PD (0x1 << 4)
400 #define CH3_PD (0x1 << 3)
401 #define CH2_PD (0x1 << 2)
402 #define CH1_PD (0x1 << 1)
403 #define CH0_PD (0x1 << 0)
406 #define MACRO_RST (0x1 << 5)
407 #define CH1_TEST (0x1 << 1)
408 #define CH0_TEST (0x1 << 0)
411 #define AUX_BUSY (0x1 << 4)
412 #define AUX_STATUS_MASK (0xf << 0)
415 #define DEFER_CTRL_EN (0x1 << 7)
416 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
419 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
420 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
423 #define BUF_CLR (0x1 << 7)
424 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
427 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
428 #define AUX_TX_COMM_MASK (0xf << 0)
429 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
430 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
431 #define AUX_TX_COMM_MOT (0x1 << 2)
432 #define AUX_TX_COMM_WRITE (0x0 << 0)
433 #define AUX_TX_COMM_READ (0x1 << 0)
436 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
439 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
442 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
445 #define ADDR_ONLY (0x1 << 1)
446 #define AUX_EN (0x1 << 0)
449 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
450 #define AUDIO_MODE_MASTER_MODE (0x0 << 8)
451 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
452 #define VIDEO_MASTER_CLK_SEL (0x1 << 2)
453 #define VIDEO_MASTER_MODE_EN (0x1 << 1)
454 #define VIDEO_MODE_MASK (0x1 << 0)
455 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
456 #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
463 #define I2C_EDID_DEVICE_ADDR 0x50
464 #define I2C_E_EDID_DEVICE_ADDR 0x30
466 #define EDID_BLOCK_LENGTH 0x80
467 #define EDID_HEADER_PATTERN 0x00
468 #define EDID_EXTENSION_FLAG 0x7e
469 #define EDID_CHECKSUM 0x7f
472 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
473 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
476 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
479 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
480 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
481 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
482 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
570 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0),