100 	lane_count = dp->link_train.lane_count;  in analogix_dp_link_start()
102 	dp->link_train.lt_state = CLOCK_RECOVERY;  in analogix_dp_link_start()
103 	dp->link_train.eq_loop = 0;  in analogix_dp_link_start()
106 		dp->link_train.cr_loop[lane] = 0;  in analogix_dp_link_start()
109 	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);  in analogix_dp_link_start()
110 	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);  in analogix_dp_link_start()
113 	buf[0] = dp->link_train.link_rate;  in analogix_dp_link_start()
114 	buf[1] = dp->link_train.lane_count;  in analogix_dp_link_start()
129 		dp->link_train.training_lane[lane] =  in analogix_dp_link_start()
218 	dp->link_train.lt_state = FAILED;  in analogix_dp_reduce_link_rate()
227 	lane_count = dp->link_train.lane_count;  in analogix_dp_get_adjust_training_lane()
241 		dp->link_train.training_lane[lane] = training_lane;  in analogix_dp_get_adjust_training_lane()
267 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_clock_recovery()
289 		dp->link_train.lt_state = EQUALIZER_TRAINING;  in analogix_dp_process_clock_recovery()
310 				dp->link_train.cr_loop[lane]++;  in analogix_dp_process_clock_recovery()
312 			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||  in analogix_dp_process_clock_recovery()
316 					dp->link_train.cr_loop[lane],  in analogix_dp_process_clock_recovery()
329 			dp->link_train.training_lane);  in analogix_dp_process_clock_recovery()
344 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_equalizer_training()
368 		dp->link_train.link_rate = reg;  in analogix_dp_process_equalizer_training()
370 		dp->link_train.lane_count = reg;  in analogix_dp_process_equalizer_training()
373 		       dp->link_train.link_rate, dp->link_train.lane_count);  in analogix_dp_process_equalizer_training()
377 		dp->link_train.lt_state = FINISHED;  in analogix_dp_process_equalizer_training()
383 	dp->link_train.eq_loop++;  in analogix_dp_process_equalizer_training()
385 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {  in analogix_dp_process_equalizer_training()
400 			lane_count, dp->link_train.training_lane);  in analogix_dp_process_equalizer_training()
446 	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);  in analogix_dp_init_training()
447 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);  in analogix_dp_init_training()
450 	dp->link_train.lane_count = min_t(u8, dp->link_train.lane_count,  in analogix_dp_init_training()
452 	dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate,  in analogix_dp_init_training()
456 	dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);  in analogix_dp_init_training()
468 	dp->link_train.lt_state = START;  in analogix_dp_sw_link_training()
472 		switch (dp->link_train.lt_state) {  in analogix_dp_sw_link_training()