Lines Matching refs:da8xx_fb_reg_base
146 static struct da8xx_lcd_regs *da8xx_fb_reg_base; variable
225 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
231 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
235 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
238 &da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
252 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
255 &da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
260 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcd_disable_raster()
262 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
268 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcd_disable_raster()
270 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
287 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
290 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
300 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
304 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
309 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
310 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
311 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
312 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
315 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
316 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
317 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
318 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
329 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
331 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
334 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
335 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
338 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
339 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
353 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; in lcd_cfg_dma()
373 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); in lcd_cfg_dma()
383 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; in lcd_cfg_ac_bias()
386 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_ac_bias()
394 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; in lcd_cfg_horizontal_sync()
398 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_horizontal_sync()
406 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; in lcd_cfg_vertical_sync()
410 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_vertical_sync()
418 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | in lcd_cfg_display()
447 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_cfg_display()
449 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_cfg_display()
452 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_display()
454 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
476 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
501 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
509 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
513 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
515 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
519 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
521 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
525 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); in lcd_cfg_frame_buffer()
535 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_frame_buffer()
634 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); in lcd_reset()
635 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); in lcd_reset()
638 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); in lcd_reset()
640 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
641 lcdc_write(0, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
658 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); in lcd_calc_clk_divider()
663 &da8xx_fb_reg_base->clk_ena); in lcd_calc_clk_divider()
678 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | in lcd_init()
680 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
682 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & in lcd_init()
684 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
721 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | in lcd_init()
722 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); in lcd_init()
731 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_dma_start()
733 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_dma_start()
735 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcdc_dma_start()
737 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcdc_dma_start()
743 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
749 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
762 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
765 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
767 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
773 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
779 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev01()
781 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev01()
791 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
797 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
799 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
811 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
814 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | in lcdc_irq_handler_rev02()
816 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); in lcdc_irq_handler_rev02()
820 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
823 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
829 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev02()
831 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev02()
833 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
836 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
902 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; in video_hw_init()
905 rev = lcdc_read(&da8xx_fb_reg_base->revid); in video_hw_init()
1011 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); in video_hw_init()
1013 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); in video_hw_init()