43 #define GT_CDCLK_337		0
57 	start = get_timer(0);  in poll32()
66 	return 0;  in poll32()
76 	writel(0x00000020, regs + 0xa180);  in haswell_early_init()
77 	writel(0x00010001, regs + 0xa188);  in haswell_early_init()
78 	ret = poll32(regs + 0x130044, 1, 1);  in haswell_early_init()
83 	setbits_le32(regs + 0xa248, 0x00000016);  in haswell_early_init()
86 	writel(0x00070020, regs + 0xa000);  in haswell_early_init()
89 	clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);  in haswell_early_init()
92 	writel(0x000003fd, regs + 0x9424);  in haswell_early_init()
95 	writel(0x00000080, regs + 0x9400);  in haswell_early_init()
96 	writel(0x40401000, regs + 0x9404);  in haswell_early_init()
97 	writel(0x00000000, regs + 0x9408);  in haswell_early_init()
98 	writel(0x02000001, regs + 0x940c);  in haswell_early_init()
105 	setbits_le32(regs + 0xa090, 0x00000000);  in haswell_early_init()
106 	setbits_le32(regs + 0xa098, 0x03e80000);  in haswell_early_init()
107 	setbits_le32(regs + 0xa09c, 0x00280000);  in haswell_early_init()
108 	setbits_le32(regs + 0xa0a8, 0x0001e848);  in haswell_early_init()
109 	setbits_le32(regs + 0xa0ac, 0x00000019);  in haswell_early_init()
112 	writel(0x0000000a, regs + 0x02054);  in haswell_early_init()
113 	writel(0x0000000a, regs + 0x12054);  in haswell_early_init()
114 	writel(0x0000000a, regs + 0x22054);  in haswell_early_init()
115 	writel(0x0000000a, regs + 0x1a054);  in haswell_early_init()
118 	setbits_le32(regs + 0xa0b0, 0x00000000);  in haswell_early_init()
119 	setbits_le32(regs + 0xa0b4, 0x000003e8);  in haswell_early_init()
120 	setbits_le32(regs + 0xa0b8, 0x0000c350);  in haswell_early_init()
123 	setbits_le32(regs + 0xa010, 0x000f4240);  in haswell_early_init()
124 	setbits_le32(regs + 0xa014, 0x12060000);  in haswell_early_init()
125 	setbits_le32(regs + 0xa02c, 0x0000e808);  in haswell_early_init()
126 	setbits_le32(regs + 0xa030, 0x0003bd08);  in haswell_early_init()
127 	setbits_le32(regs + 0xa068, 0x000101d0);  in haswell_early_init()
128 	setbits_le32(regs + 0xa06c, 0x00055730);  in haswell_early_init()
129 	setbits_le32(regs + 0xa070, 0x0000000a);  in haswell_early_init()
132 	writel(0x00000b92, regs + 0xa024);  in haswell_early_init()
135 	writel(0x88040000, regs + 0xa090);  in haswell_early_init()
138 	writel(0x08000000, regs + 0xa00c);  in haswell_early_init()
141 	ret = poll32(regs + 0x138124, (1 << 31), 0);  in haswell_early_init()
144 	writel(0, regs + 0x138128);  in haswell_early_init()
145 	writel(0x80000004, regs + 0x138124);  in haswell_early_init()
146 	ret = poll32(regs + 0x138124, (1 << 31), 0);  in haswell_early_init()
151 	writel(0x03000076, regs + 0x4402c);  in haswell_early_init()
154 	writel(0x00040000, regs + 0xa094);  in haswell_early_init()
156 	return 0;  in haswell_early_init()
169 	setbits_le32(regs + 0x0a248, (1 << 31));  in haswell_late_init()
170 	setbits_le32(regs + 0x0a004, (1 << 4));  in haswell_late_init()
171 	setbits_le32(regs + 0x0a080, (1 << 2));  in haswell_late_init()
172 	setbits_le32(regs + 0x0a180, (1 << 31));  in haswell_late_init()
175 	writel(0x00010000, regs + 0xa188);  in haswell_late_init()
176 	ret = poll32(regs + 0x130044, 1, 0);  in haswell_late_init()
179 	writel(0x00000001, regs + 0xa188);  in haswell_late_init()
182 	setbits_le32(regs + 0x45400, (1 << 31));  in haswell_late_init()
183 	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);  in haswell_late_init()
187 	return 0;  in haswell_late_init()
200 	writel(0x00010001, regs + 0xa188);  in broadwell_early_init()
201 	ret = poll32(regs + 0x130044, 1, 1);  in broadwell_early_init()
206 	writel(0x00000004, regs + 0xa248);  in broadwell_early_init()
207 	writel(0x000000ff, regs + 0xa250);  in broadwell_early_init()
208 	writel(0x00000010, regs + 0xa25c);  in broadwell_early_init()
213 	writel(0x45200000, regs + 0xa180);  in broadwell_early_init()
216 	writel(0x000000fd, regs + 0x9424);  in broadwell_early_init()
219 	writel(0x00000000, regs + 0x9400);  in broadwell_early_init()
220 	writel(0x40401000, regs + 0x9404);  in broadwell_early_init()
221 	writel(0x00000000, regs + 0x9408);  in broadwell_early_init()
222 	writel(0x02000001, regs + 0x940c);  in broadwell_early_init()
223 	writel(0x0000000a, regs + 0x1a054);  in broadwell_early_init()
226 	writel(0x08000000, regs + 0xa00c);  in broadwell_early_init()
228 	writel(0x00000009, regs + 0x138158);  in broadwell_early_init()
229 	writel(0x0000000d, regs + 0x13815c);  in broadwell_early_init()
236 	clrsetbits_le32(regs + 0x0a090, ~0, 0);  in broadwell_early_init()
237 	setbits_le32(regs + 0x0a098, 0x03e80000);  in broadwell_early_init()
238 	setbits_le32(regs + 0x0a09c, 0x00280000);  in broadwell_early_init()
239 	setbits_le32(regs + 0x0a0a8, 0x0001e848);  in broadwell_early_init()
240 	setbits_le32(regs + 0x0a0ac, 0x00000019);  in broadwell_early_init()
243 	writel(0x0000000a, regs + 0x02054);  in broadwell_early_init()
244 	writel(0x0000000a, regs + 0x12054);  in broadwell_early_init()
245 	writel(0x0000000a, regs + 0x22054);  in broadwell_early_init()
248 	setbits_le32(regs + 0x0a0b0, 0x00000000);  in broadwell_early_init()
249 	setbits_le32(regs + 0x0a0b8, 0x00000271);  in broadwell_early_init()
252 	setbits_le32(regs + 0x0a010, 0x000f4240);  in broadwell_early_init()
253 	setbits_le32(regs + 0x0a014, 0x12060000);  in broadwell_early_init()
254 	setbits_le32(regs + 0x0a02c, 0x0000e808);  in broadwell_early_init()
255 	setbits_le32(regs + 0x0a030, 0x0003bd08);  in broadwell_early_init()
256 	setbits_le32(regs + 0x0a068, 0x000101d0);  in broadwell_early_init()
257 	setbits_le32(regs + 0x0a06c, 0x00055730);  in broadwell_early_init()
258 	setbits_le32(regs + 0x0a070, 0x0000000a);  in broadwell_early_init()
259 	setbits_le32(regs + 0x0a168, 0x00000006);  in broadwell_early_init()
262 	writel(0x00000b92, regs + 0xa024);  in broadwell_early_init()
265 	writel(0x90040000, regs + 0xa090);  in broadwell_early_init()
268 	ret = poll32(regs + 0x138124, (1 << 31), 0);  in broadwell_early_init()
271 	writel(0, regs + 0x138128);  in broadwell_early_init()
272 	writel(0x80000004, regs + 0x138124);  in broadwell_early_init()
273 	ret = poll32(regs + 0x138124, (1 << 31), 0);  in broadwell_early_init()
278 	writel(0x03000076, regs + 0x4402c);  in broadwell_early_init()
281 	writel(0x00040000, regs + 0xa094);  in broadwell_early_init()
283 	return 0;  in broadwell_early_init()
296 	setbits_le32(regs + 0x0a248, 1 << 31);  in broadwell_late_init()
297 	setbits_le32(regs + 0x0a000, 1 << 18);  in broadwell_late_init()
298 	setbits_le32(regs + 0x0a180, 1 << 31);  in broadwell_late_init()
301 	writel(0x00010000, regs + 0xa188);  in broadwell_late_init()
302 	ret = poll32(regs + 0x130044, 1, 0);  in broadwell_late_init()
307 	setbits_le32(regs + 0x45400, 1 << 31);  in broadwell_late_init()
308 	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);  in broadwell_late_init()
312 	return 0;  in broadwell_late_init()
346 			return 0;  in gtt_poll()
361 	reg32 = (plat->dp_hotplug[0] & 0x7) << 2;  in igd_setup_panel()
362 	reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;  in igd_setup_panel()
363 	reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;  in igd_setup_panel()
367 	reg32 = (plat->port_select & 0x3) << 30;  in igd_setup_panel()
368 	reg32 |= (plat->power_up_delay & 0x1fff) << 16;  in igd_setup_panel()
369 	reg32 |= (plat->power_backlight_on_delay & 0x1fff);  in igd_setup_panel()
373 	reg32 = (plat->power_down_delay & 0x1fff) << 16;  in igd_setup_panel()
374 	reg32 |= (plat->power_backlight_off_delay & 0x1fff);  in igd_setup_panel()
380 		reg32 &= ~0xff;  in igd_setup_panel()
381 		reg32 |= plat->power_cycle_delay & 0xff;  in igd_setup_panel()
402 	int gpu_is_ulx = 0;  in igd_cdclk_init_haswell()
409 	if (devid == 0x0a0e || devid == 0x0a1e)  in igd_cdclk_init_haswell()
417 	if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())  in igd_cdclk_init_haswell()
436 		lpcll = 0;  in igd_cdclk_init_haswell()
448 	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);  in igd_cdclk_init_haswell()
453 			gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */  in igd_cdclk_init_haswell()
455 			gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */  in igd_cdclk_init_haswell()
456 		gtt_write(priv, 0x13812c, 0x00000000);  in igd_cdclk_init_haswell()
457 		gtt_write(priv, 0x138124, 0x80000017);  in igd_cdclk_init_haswell()
461 	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);  in igd_cdclk_init_haswell()
462 	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);  in igd_cdclk_init_haswell()
464 	return 0;  in igd_cdclk_init_haswell()
479 	gtt_write(priv, 0x138128, 0);  in igd_cdclk_init_broadwell()
480 	gtt_write(priv, 0x13812c, 0);  in igd_cdclk_init_broadwell()
481 	gtt_write(priv, 0x138124, 0x80000018);  in igd_cdclk_init_broadwell()
484 	if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))  in igd_cdclk_init_broadwell()
487 	if (gtt_read(priv, 0x42014) & 0x1000000) {  in igd_cdclk_init_broadwell()
512 		lpcll = 0;  in igd_cdclk_init_broadwell()
513 		pwctl = 0;  in igd_cdclk_init_broadwell()
535 	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);  in igd_cdclk_init_broadwell()
538 	gtt_write(priv, 0x138128, pwctl);  in igd_cdclk_init_broadwell()
539 	gtt_write(priv, 0x13812c, 0);  in igd_cdclk_init_broadwell()
540 	gtt_write(priv, 0x138124, 0x80000017);  in igd_cdclk_init_broadwell()
543 	gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);  in igd_cdclk_init_broadwell()
546 	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);  in igd_cdclk_init_broadwell()
547 	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);  in igd_cdclk_init_broadwell()
549 	return 0;  in igd_cdclk_init_broadwell()
559 	pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,  in systemagent_revision()
581 		if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&  in igd_pre_init()
583 			gtt_write(priv, 0xa000, 0x300ff);  in igd_pre_init()
585 			gtt_write(priv, 0xa000, 0x30020);  in igd_pre_init()
594 	rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;  in igd_pre_init()
595 	gtt_write(priv, 0xa008, rp1_gfx_freq << 24);  in igd_pre_init()
600 	return 0;  in igd_pre_init()
625 	return 0;  in igd_post_init()
630 	int res = 0;  in broadwell_igd_int15_handler()
635 	case 0x5f35:  in broadwell_igd_int15_handler()
638 		 *  bit 0 = CRT  in broadwell_igd_int15_handler()
647 		M.x86.R_AX = 0x005f;  in broadwell_igd_int15_handler()
648 		M.x86.R_CX = 0x0000; /* Use video bios default */  in broadwell_igd_int15_handler()
701 	return 0;  in broadwell_igd_probe()
715 	plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);  in broadwell_igd_ofdata_to_platdata()
717 			"intel,power-cycle-delay", 0);  in broadwell_igd_ofdata_to_platdata()
719 			"intel,power-up-delay", 0);  in broadwell_igd_ofdata_to_platdata()
721 			"intel,power-down-delay", 0);  in broadwell_igd_ofdata_to_platdata()
723 			"intel,power-backlight-on-delay", 0);  in broadwell_igd_ofdata_to_platdata()
725 			"intel,power-backlight-off-delay", 0);  in broadwell_igd_ofdata_to_platdata()
727 			"intel,cpu-backlight", 0);  in broadwell_igd_ofdata_to_platdata()
729 			"intel,pch-backlight", 0);  in broadwell_igd_ofdata_to_platdata()
731 			"intel,pre-graphics-delay", 0);  in broadwell_igd_ofdata_to_platdata()
732 	priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);  in broadwell_igd_ofdata_to_platdata()
734 	debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],  in broadwell_igd_ofdata_to_platdata()
749 	return 0;  in broadwell_igd_ofdata_to_platdata()