Lines Matching full:mode
199 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) in radeon_write_pll_regs() argument
215 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
216 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
222 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
242 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
250 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
251 /* When restoring console mode, use saved PPLL_REF_DIV in radeon_write_pll_regs()
254 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
258 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
262 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
265 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
266 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
300 /* these common regs are cleared before mode setting so they do not
319 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); in radeon_setmode() local
321 mode->crtc_gen_cntl = 0x03000200; in radeon_setmode()
322 mode->crtc_ext_cntl = 0x00008048; in radeon_setmode()
323 mode->dac_cntl = 0xff002100; in radeon_setmode()
324 mode->crtc_h_total_disp = 0x4f0063; in radeon_setmode()
325 mode->crtc_h_sync_strt_wid = 0x8c02a2; in radeon_setmode()
326 mode->crtc_v_total_disp = 0x01df020c; in radeon_setmode()
327 mode->crtc_v_sync_strt_wid = 0x8201ea; in radeon_setmode()
328 mode->crtc_pitch = 0x00500050; in radeon_setmode()
330 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_setmode()
331 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode()
333 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_setmode()
334 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_setmode()
335 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_setmode()
336 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_setmode()
337 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_setmode()
340 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_setmode()
342 mode->clk_cntl_index = 0x300; in radeon_setmode()
343 mode->ppll_ref_div = 0xc; in radeon_setmode()
344 mode->ppll_div_3 = 0x00030059; in radeon_setmode()
346 radeon_write_pll_regs(rinfo, mode); in radeon_setmode()
362 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); in radeon_setmode_9200() local
364 mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; in radeon_setmode_9200()
365 mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; in radeon_setmode_9200()
366 mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; in radeon_setmode_9200()
367 mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; in radeon_setmode_9200()
371 mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ in radeon_setmode_9200()
373 mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; in radeon_setmode_9200()
374 mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; in radeon_setmode_9200()
378 mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ in radeon_setmode_9200()
380 mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; in radeon_setmode_9200()
381 mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; in radeon_setmode_9200()
385 mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ in radeon_setmode_9200()
386 mode->surface_cntl = 0x00000000; in radeon_setmode_9200()
392 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); in radeon_setmode_9200()
393 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); in radeon_setmode_9200()
394 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200()
396 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); in radeon_setmode_9200()
397 mode->ppll_div_3 = 0x00010078; in radeon_setmode_9200()
399 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); in radeon_setmode_9200()
400 mode->ppll_div_3 = 0x00010060; in radeon_setmode_9200()
403 * for this mode pitch expands to the same value for 32, 16 and 8 bpp, in radeon_setmode_9200()
406 mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); in radeon_setmode_9200()
409 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); in radeon_setmode_9200()
410 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); in radeon_setmode_9200()
413 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); in radeon_setmode_9200()
414 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); in radeon_setmode_9200()
417 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); in radeon_setmode_9200()
418 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); in radeon_setmode_9200()
424 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); in radeon_setmode_9200()
425 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); in radeon_setmode_9200()
426 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); in radeon_setmode_9200()
427 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200()
428 mode->ppll_div_3 = 0x0002008c; in radeon_setmode_9200()
430 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); in radeon_setmode_9200()
431 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
432 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); in radeon_setmode_9200()
433 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
434 mode->ppll_div_3 = 0x00020074; in radeon_setmode_9200()
437 mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); in radeon_setmode_9200()
440 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); in radeon_setmode_9200()
441 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); in radeon_setmode_9200()
444 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); in radeon_setmode_9200()
445 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); in radeon_setmode_9200()
448 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
449 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); in radeon_setmode_9200()
454 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); in radeon_setmode_9200()
456 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); in radeon_setmode_9200()
457 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); in radeon_setmode_9200()
458 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200()
459 mode->ppll_div_3 = 0x000300b0; in radeon_setmode_9200()
461 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); in radeon_setmode_9200()
462 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); in radeon_setmode_9200()
463 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200()
464 mode->ppll_div_3 = 0x0003008e; in radeon_setmode_9200()
468 mode->crtc_pitch = RADEON_CRT_PITCH(832,32); in radeon_setmode_9200()
469 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); in radeon_setmode_9200()
470 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); in radeon_setmode_9200()
473 mode->crtc_pitch = RADEON_CRT_PITCH(896,16); in radeon_setmode_9200()
474 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); in radeon_setmode_9200()
475 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); in radeon_setmode_9200()
478 mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); in radeon_setmode_9200()
479 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
480 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); in radeon_setmode_9200()
486 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); in radeon_setmode_9200()
487 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
488 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); in radeon_setmode_9200()
489 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
490 mode->ppll_div_3 = 0x00030070; in radeon_setmode_9200()
492 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); in radeon_setmode_9200()
493 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
494 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); in radeon_setmode_9200()
495 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
496 mode->ppll_div_3 = 0x00030059; in radeon_setmode_9200()
499 mode->crtc_pitch = RADEON_CRT_PITCH(640,32); in radeon_setmode_9200()
502 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); in radeon_setmode_9200()
503 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); in radeon_setmode_9200()
506 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); in radeon_setmode_9200()
507 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); in radeon_setmode_9200()
510 mode->crtc_offset_cntl = 0x00000000; in radeon_setmode_9200()
516 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); in radeon_setmode_9200()
517 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode_9200()
519 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_setmode_9200()
520 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_setmode_9200()
521 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_setmode_9200()
522 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_setmode_9200()
523 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_setmode_9200()
525 OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); in radeon_setmode_9200()
526 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_setmode_9200()
527 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_setmode_9200()
529 mode->clk_cntl_index = 0x300; in radeon_setmode_9200()
530 mode->ppll_ref_div = 0xc; in radeon_setmode_9200()
532 radeon_write_pll_regs(rinfo, mode); in radeon_setmode_9200()
534 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode_9200()
536 OUTREG(SURFACE0_INFO, mode->surf_info[0]); in radeon_setmode_9200()
538 OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); in radeon_setmode_9200()
539 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_setmode_9200()
544 free(mode); in radeon_setmode_9200()
639 /* get video mode via environment */ in video_hw_init()
658 printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); in video_hw_init()