26  * @data_rate:	Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
38 		colordepth = 0x00; /* 6 bit */  in anx9804_init()
40 		colordepth = 0x10; /* 8 bit */  in anx9804_init()
43 	i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);  in anx9804_init()
45 	i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);  in anx9804_init()
47 	/* Write 0 to the powerdown reg (powerup everything) */  in anx9804_init()
48 	i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);  in anx9804_init()
50 	c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);  in anx9804_init()
51 	if (c != 0x98) {  in anx9804_init()
57 	for (i = 0; i < 100; i++) {  in anx9804_init()
58 		c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);  in anx9804_init()
59 		i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);  in anx9804_init()
60 		c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);  in anx9804_init()
61 		if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)  in anx9804_init()
69 	i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);  in anx9804_init()
72 	i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);   in anx9804_init()
73 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);   in anx9804_init()
74 	i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);   in anx9804_init()
75 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);  in anx9804_init()
76 	i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);  in anx9804_init()
77 	i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);  in anx9804_init()
78 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);  in anx9804_init()
79 	i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);  in anx9804_init()
80 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);  in anx9804_init()
83 	i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,  in anx9804_init()
87 	i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);  in anx9804_init()
88 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);  in anx9804_init()
89 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);  in anx9804_init()
90 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);  in anx9804_init()
91 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);  in anx9804_init()
94 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,  in anx9804_init()
96 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,  in anx9804_init()
100 	i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);  in anx9804_init()
101 	i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);  in anx9804_init()
102 	i2c_reg_write(0x38, 0xa7, 0x00);  in anx9804_init()
105 	i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);  in anx9804_init()
106 	i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);  in anx9804_init()
109 	i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,  in anx9804_init()
112 	for (i = 0; i < 100; i++) {  in anx9804_init()
113 		c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);  in anx9804_init()
114 		if ((c & 0x01) == 0)  in anx9804_init()
126 	i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,  in anx9804_init()
129 	i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,  in anx9804_init()