44 		csr = readw(&musbr->txcsr);  in write_toggle()
50 			writew(csr, &musbr->txcsr);  in write_toggle()
53 			writew(csr, &musbr->txcsr);  in write_toggle()
55 			writew(csr, &musbr->txcsr);  in write_toggle()
59 			csr = readw(&musbr->txcsr);  in write_toggle()
86 		csr = readw(&musbr->txcsr);  in check_stall()
89 			writew(csr, &musbr->txcsr);  in check_stall()
94 			csr = readw(&musbr->txcsr);  in check_stall()
97 				writew(csr, &musbr->txcsr);  in check_stall()
123 		csr = readw(&musbr->txcsr);  in wait_until_ep0_ready()
126 			writew(csr, &musbr->txcsr);  in wait_until_ep0_ready()
190 		csr = readw(&musbr->txcsr);  in wait_until_txep_ready()
252 	csr = readw(&musbr->txcsr);  in ctrlreq_setup_phase()
254 	writew(csr, &musbr->txcsr);  in ctrlreq_setup_phase()
280 		csr = readw(&musbr->txcsr);  in ctrlreq_in_data_phase()
281 		writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);  in ctrlreq_in_data_phase()
293 		csr = readw(&musbr->txcsr);  in ctrlreq_in_data_phase()
295 		writew(csr, &musbr->txcsr);  in ctrlreq_in_data_phase()
328 		csr = readw(&musbr->txcsr);  in ctrlreq_out_data_phase()
334 		writew(csr, &musbr->txcsr);  in ctrlreq_out_data_phase()
354 	csr = readw(&musbr->txcsr);  in ctrlreq_out_status_phase()
359 	writew(csr, &musbr->txcsr);  in ctrlreq_out_status_phase()
379 	writew(csr, &musbr->txcsr);  in ctrlreq_in_status_phase()
383 	csr = readw(&musbr->txcsr);  in ctrlreq_in_status_phase()
385 	writew(csr, &musbr->txcsr);  in ctrlreq_in_status_phase()
770 	readw(&musbr->txcsr);  in submit_control_msg()
921 			csr = readw(&musbr->txcsr);  in submit_bulk_msg()
922 			writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);  in submit_bulk_msg()
926 				readw(&musbr->txcsr);  in submit_bulk_msg()
936 		csr = readw(&musbr->txcsr);  in submit_bulk_msg()