Lines Matching refs:csr
41 u16 csr; in write_toggle() local
44 csr = readw(&musbr->txcsr); in write_toggle()
46 if (csr & MUSB_TXCSR_MODE) in write_toggle()
47 csr = MUSB_TXCSR_CLRDATATOG; in write_toggle()
49 csr = 0; in write_toggle()
50 writew(csr, &musbr->txcsr); in write_toggle()
52 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; in write_toggle()
53 writew(csr, &musbr->txcsr); in write_toggle()
54 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); in write_toggle()
55 writew(csr, &musbr->txcsr); in write_toggle()
59 csr = readw(&musbr->txcsr); in write_toggle()
60 if (csr & MUSB_TXCSR_MODE) in write_toggle()
61 csr = MUSB_RXCSR_CLRDATATOG; in write_toggle()
63 csr = 0; in write_toggle()
64 writew(csr, &musbr->rxcsr); in write_toggle()
66 csr = readw(&musbr->rxcsr); in write_toggle()
67 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; in write_toggle()
68 writew(csr, &musbr->rxcsr); in write_toggle()
69 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); in write_toggle()
70 writew(csr, &musbr->rxcsr); in write_toggle()
82 u16 csr; in check_stall() local
86 csr = readw(&musbr->txcsr); in check_stall()
87 if (csr & MUSB_CSR0_H_RXSTALL) { in check_stall()
88 csr &= ~MUSB_CSR0_H_RXSTALL; in check_stall()
89 writew(csr, &musbr->txcsr); in check_stall()
94 csr = readw(&musbr->txcsr); in check_stall()
95 if (csr & MUSB_TXCSR_H_RXSTALL) { in check_stall()
96 csr &= ~MUSB_TXCSR_H_RXSTALL; in check_stall()
97 writew(csr, &musbr->txcsr); in check_stall()
101 csr = readw(&musbr->rxcsr); in check_stall()
102 if (csr & MUSB_RXCSR_H_RXSTALL) { in check_stall()
103 csr &= ~MUSB_RXCSR_H_RXSTALL; in check_stall()
104 writew(csr, &musbr->rxcsr); in check_stall()
118 u16 csr; in wait_until_ep0_ready() local
123 csr = readw(&musbr->txcsr); in wait_until_ep0_ready()
124 if (csr & MUSB_CSR0_H_ERROR) { in wait_until_ep0_ready()
125 csr &= ~MUSB_CSR0_H_ERROR; in wait_until_ep0_ready()
126 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
134 if (!(csr & MUSB_CSR0_TXPKTRDY)) { in wait_until_ep0_ready()
148 if (csr & MUSB_CSR0_RXPKTRDY) in wait_until_ep0_ready()
153 if (!(csr & MUSB_CSR0_H_REQPKT)) { in wait_until_ep0_ready()
181 u16 csr; in wait_until_txep_ready() local
190 csr = readw(&musbr->txcsr); in wait_until_txep_ready()
191 if (csr & MUSB_TXCSR_H_ERROR) { in wait_until_txep_ready()
204 } while (csr & MUSB_TXCSR_TXPKTRDY); in wait_until_txep_ready()
213 u16 csr; in wait_until_rxep_ready() local
222 csr = readw(&musbr->rxcsr); in wait_until_rxep_ready()
223 if (csr & MUSB_RXCSR_H_ERROR) { in wait_until_rxep_ready()
236 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); in wait_until_rxep_ready()
246 u16 csr; in ctrlreq_setup_phase() local
252 csr = readw(&musbr->txcsr); in ctrlreq_setup_phase()
253 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); in ctrlreq_setup_phase()
254 writew(csr, &musbr->txcsr); in ctrlreq_setup_phase()
267 u16 csr; in ctrlreq_in_data_phase() local
280 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
281 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); in ctrlreq_in_data_phase()
293 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
294 csr &= ~MUSB_CSR0_RXPKTRDY; in ctrlreq_in_data_phase()
295 writew(csr, &musbr->txcsr); in ctrlreq_in_data_phase()
313 u16 csr; in ctrlreq_out_data_phase() local
328 csr = readw(&musbr->txcsr); in ctrlreq_out_data_phase()
330 csr |= MUSB_CSR0_TXPKTRDY; in ctrlreq_out_data_phase()
332 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_data_phase()
334 writew(csr, &musbr->txcsr); in ctrlreq_out_data_phase()
350 u16 csr; in ctrlreq_out_status_phase() local
354 csr = readw(&musbr->txcsr); in ctrlreq_out_status_phase()
355 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_out_status_phase()
357 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_status_phase()
359 writew(csr, &musbr->txcsr); in ctrlreq_out_status_phase()
371 u16 csr; in ctrlreq_in_status_phase() local
375 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; in ctrlreq_in_status_phase()
377 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_in_status_phase()
379 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
383 csr = readw(&musbr->txcsr); in ctrlreq_in_status_phase()
384 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_in_status_phase()
385 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
861 u16 csr; in submit_bulk_msg() local
921 csr = readw(&musbr->txcsr); in submit_bulk_msg()
922 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); in submit_bulk_msg()
928 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
936 csr = readw(&musbr->txcsr); in submit_bulk_msg()
938 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
956 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
957 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_bulk_msg()
961 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
963 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
964 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
965 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
975 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
976 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
977 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
982 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
984 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
1068 u16 csr; in submit_int_msg() local
1129 csr = readw(&musbr->rxcsr); in submit_int_msg()
1130 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_int_msg()
1134 csr = readw(&musbr->rxcsr); in submit_int_msg()
1136 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()
1137 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1138 writew(csr, &musbr->rxcsr); in submit_int_msg()
1148 csr = readw(&musbr->rxcsr); in submit_int_msg()
1149 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1150 writew(csr, &musbr->rxcsr); in submit_int_msg()
1155 csr = readw(&musbr->rxcsr); in submit_int_msg()
1157 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()