Lines Matching refs:hw_ep
197 struct musb_hw_ep *hw_ep = qh->hw_ep; in musb_start_urb() local
200 int epnum = hw_ep->epnum; in musb_start_urb()
243 musb_ep_set_qh(hw_ep, is_in, qh); in musb_start_urb()
284 hw_ep->tx_channel ? "dma" : "pio"); in musb_start_urb()
286 if (!hw_ep->tx_channel) in musb_start_urb()
287 musb_h_tx_start(hw_ep); in musb_start_urb()
289 musb_h_tx_dma_start(hw_ep); in musb_start_urb()
317 void __iomem *epio = qh->hw_ep->regs; in musb_save_toggle()
341 struct musb_hw_ep *hw_ep, int is_in) in musb_advance_schedule() argument
343 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); in musb_advance_schedule()
344 struct musb_hw_ep *ep = qh->hw_ep; in musb_advance_schedule()
422 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); in musb_advance_schedule()
427 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) in musb_h_flush_rxfifo() argument
439 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
440 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
443 return musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_h_flush_rxfifo()
458 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_packet_rx() local
459 void __iomem *epio = hw_ep->regs; in musb_host_packet_rx()
460 struct musb_qh *qh = hw_ep->in_qh; in musb_host_packet_rx()
529 musb_read_fifo(hw_ep, length, buf); in musb_host_packet_rx()
534 musb_h_flush_rxfifo(hw_ep, csr); in musb_host_packet_rx()
618 struct musb_hw_ep *hw_ep, struct musb_qh *qh, in musb_tx_dma_program() argument
621 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_program()
622 void __iomem *epio = hw_ep->regs; in musb_tx_dma_program()
669 hw_ep->tx_channel = NULL; in musb_tx_dma_program()
691 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_ep_program() local
692 void __iomem *epio = hw_ep->regs; in musb_ep_program()
693 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); in musb_ep_program()
709 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; in musb_ep_program()
712 dma_controller, hw_ep, is_out); in musb_ep_program()
714 hw_ep->tx_channel = dma_channel; in musb_ep_program()
716 hw_ep->rx_channel = dma_channel; in musb_ep_program()
738 musb_h_tx_flush_fifo(hw_ep); in musb_ep_program()
768 musb_h_ep0_flush_fifo(hw_ep); in musb_ep_program()
785 hw_ep->max_packet_sz_tx); in musb_ep_program()
788 | ((hw_ep->max_packet_sz_tx / in musb_ep_program()
803 load_count = min((u32) hw_ep->max_packet_sz_tx, in musb_ep_program()
809 hw_ep, qh, urb, offset, len)) in musb_ep_program()
815 musb_write_fifo(hw_ep, load_count, buf); in musb_ep_program()
825 if (hw_ep->rx_reinit) { in musb_ep_program()
826 musb_rx_reinit(musb, qh, hw_ep); in musb_ep_program()
838 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
844 hw_ep->epnum, csr); in musb_ep_program()
858 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
859 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
872 hw_ep->rx_channel = dma_channel = NULL; in musb_ep_program()
879 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
880 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
894 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_continue() local
895 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_continue()
906 musb_read_fifo(hw_ep, fifo_count, fifo_dest); in musb_h_ep0_continue()
945 musb_write_fifo(hw_ep, fifo_count, fifo_dest); in musb_h_ep0_continue()
971 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_irq() local
972 void __iomem *epio = hw_ep->regs; in musb_h_ep0_irq()
973 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_irq()
1033 musb_h_ep0_flush_fifo(hw_ep); in musb_h_ep0_irq()
1047 musb_h_ep0_flush_fifo(hw_ep); in musb_h_ep0_irq()
1080 musb_advance_schedule(musb, urb, hw_ep, 1); in musb_h_ep0_irq()
1110 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_tx() local
1111 void __iomem *epio = hw_ep->regs; in musb_host_tx()
1112 struct musb_qh *qh = hw_ep->out_qh; in musb_host_tx()
1129 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; in musb_host_tx()
1174 musb_h_tx_flush_fifo(hw_ep); in musb_host_tx()
1311 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); in musb_host_tx()
1314 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, in musb_host_tx()
1317 musb_h_tx_dma_start(hw_ep); in musb_host_tx()
1336 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); in musb_host_tx()
1435 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_rx() local
1436 void __iomem *epio = hw_ep->regs; in musb_host_rx()
1437 struct musb_qh *qh = hw_ep->in_qh; in musb_host_rx()
1450 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; in musb_host_rx()
1464 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); in musb_host_rx()
1504 musb_bulk_rx_nak_timeout(musb, hw_ep); in musb_host_rx()
1532 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); in musb_host_rx()
1581 musb_writew(hw_ep->regs, MUSB_RXCSR, val); in musb_host_rx()
1697 if (rx_count < hw_ep->max_packet_sz_rx) { in musb_host_rx()
1748 hw_ep->rx_channel = NULL; in musb_host_rx()
1774 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); in musb_host_rx()
1791 struct musb_hw_ep *hw_ep = NULL; in musb_schedule() local
1800 hw_ep = musb->control_ep; in musb_schedule()
1816 for (epnum = 1, hw_ep = musb->endpoints + 1; in musb_schedule()
1818 epnum++, hw_ep++) { in musb_schedule()
1821 if (musb_ep_get_qh(hw_ep, is_in) != NULL) in musb_schedule()
1824 if (hw_ep == musb->bulk_ep) in musb_schedule()
1828 diff = hw_ep->max_packet_sz_rx; in musb_schedule()
1830 diff = hw_ep->max_packet_sz_tx; in musb_schedule()
1847 hw_ep = musb->endpoints + epnum; in musb_schedule()
1849 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) in musb_schedule()
1861 hw_ep = musb->bulk_ep; in musb_schedule()
1884 hw_ep = musb->endpoints + best_end; in musb_schedule()
1892 qh->hw_ep = hw_ep; in musb_schedule()
2124 struct musb_hw_ep *ep = qh->hw_ep;
2223 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2266 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2282 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);