Lines Matching +full:oscillator +full:- +full:stable +full:- +full:time
3 * Copyright (c) 2009-2015 NVIDIA Corporation
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm-generic/gpio.h>
15 #include <asm/arch-tegra/usb.h>
16 #include <asm/arch-tegra/clk_rst.h>
44 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
45 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
46 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
47 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
88 * This table has USB timing parameters for each Oscillator frequency we
92 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
95 * ----------------------------------------------------------------------
105 * ---------------------------------------------------------------------------
117 * 0xffff -> No debouncing at all
211 struct fdt_usb *config = ctrl->priv; in tegra_ehci_powerup_fixup()
214 controller = &fdt_usb_controllers[config->type]; in tegra_ehci_powerup_fixup()
216 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ in tegra_ehci_powerup_fixup()
217 if (controller->has_hostpc) in tegra_ehci_powerup_fixup()
220 if (!config->has_legacy_mode) in tegra_ehci_powerup_fixup()
229 struct fdt_usb *config = ctrl->priv; in tegra_ehci_set_usbmode()
233 usbctlr = config->reg; in tegra_ehci_set_usbmode()
235 tmp = ehci_readl(&usbctlr->usb_mode); in tegra_ehci_set_usbmode()
237 ehci_writel(&usbctlr->usb_mode, tmp); in tegra_ehci_set_usbmode()
242 struct fdt_usb *config = ctrl->priv; in tegra_ehci_get_port_speed()
247 controller = &fdt_usb_controllers[config->type]; in tegra_ehci_get_port_speed()
248 if (controller->has_hostpc) { in tegra_ehci_get_port_speed()
249 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + in tegra_ehci_get_port_speed()
265 config->dr_mode == DR_MODE_OTG && in set_up_vbus()
266 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { in set_up_vbus()
271 if (dm_gpio_is_valid(&config->vbus_gpio)) { in set_up_vbus()
275 dm_gpio_set_value(&config->vbus_gpio, vbus_value); in set_up_vbus()
278 gpio_get_number(&config->vbus_gpio), vbus_value); in set_up_vbus()
286 reset_periph(config->periph_id, 2); in usbf_reset_controller()
292 if (config->has_legacy_mode) in usbf_reset_controller()
293 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); in usbf_reset_controller()
296 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); in usbf_reset_controller()
299 if (config->utmi) in usbf_reset_controller()
300 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); in usbf_reset_controller()
307 timing = controller->pll_parameter + in get_pll_timing()
317 struct usb_ctlr *usbctlr = config->reg; in init_phy_mux()
320 if (config->periph_id == PERIPH_ID_USBD) { in init_phy_mux()
321 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, in init_phy_mux()
323 clrbits_le32(&usbctlr->port_sc1, STS1); in init_phy_mux()
325 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, in init_phy_mux()
327 clrbits_le32(&usbctlr->port_sc1, STS); in init_phy_mux()
331 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, in init_phy_mux()
338 * already made at reset time, so this write is a no-op. in init_phy_mux()
340 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, in init_phy_mux()
342 clrbits_le32(&usbctlr->hostpc1_devlc, STS); in init_phy_mux()
354 struct usb_ctlr *usbctlr = config->reg; in init_utmi_usb_controller()
358 clock_enable(config->periph_id); in init_utmi_usb_controller()
364 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
370 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, in init_utmi_usb_controller()
377 if (config->dr_mode == DR_MODE_OTG && in init_utmi_usb_controller()
378 dm_gpio_is_valid(&config->vbus_gpio)) in init_utmi_usb_controller()
379 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, in init_utmi_usb_controller()
383 controller = &fdt_usb_controllers[config->type]; in init_utmi_usb_controller()
384 debug("controller=%p, type=%d\n", controller, config->type); in init_utmi_usb_controller()
392 if (!controller->has_hostpc) { in init_utmi_usb_controller()
393 val = readl(&usbctlr->utmip_misc_cfg1); in init_utmi_usb_controller()
400 writel(val, &usbctlr->utmip_misc_cfg1); in init_utmi_usb_controller()
403 val = readl(&usbctlr->utmip_pll_cfg1); in init_utmi_usb_controller()
410 writel(val, &usbctlr->utmip_pll_cfg1); in init_utmi_usb_controller()
414 val = readl(&clkrst->crc_utmip_pll_cfg2); in init_utmi_usb_controller()
421 writel(val, &clkrst->crc_utmip_pll_cfg2); in init_utmi_usb_controller()
424 val = readl(&clkrst->crc_utmip_pll_cfg1); in init_utmi_usb_controller()
431 writel(val, &clkrst->crc_utmip_pll_cfg1); in init_utmi_usb_controller()
434 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, in init_utmi_usb_controller()
439 val = readl(&usbctlr->utmip_xcvr_cfg0); in init_utmi_usb_controller()
446 writel(val, &usbctlr->utmip_xcvr_cfg0); in init_utmi_usb_controller()
447 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, in init_utmi_usb_controller()
452 if (config->periph_id != PERIPH_ID_USBD) { in init_utmi_usb_controller()
458 ((unsigned long)config->reg & USB1_ADDR_MASK); in init_utmi_usb_controller()
459 val = readl(&usb1ctlr->utmip_bias_cfg0); in init_utmi_usb_controller()
465 writel(val, &usb1ctlr->utmip_bias_cfg0); in init_utmi_usb_controller()
468 clrbits_le32(&usbctlr->utmip_misc_cfg0, in init_utmi_usb_controller()
472 /* Setting the tracking length time */ in init_utmi_usb_controller()
473 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
477 /* Program debounce time for VBUS to become valid */ in init_utmi_usb_controller()
478 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, in init_utmi_usb_controller()
483 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, in init_utmi_usb_controller()
487 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
492 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); in init_utmi_usb_controller()
495 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); in init_utmi_usb_controller()
497 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); in init_utmi_usb_controller()
498 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); in init_utmi_usb_controller()
510 val = readl(&usbctlr->utmip_hsrx_cfg0); in init_utmi_usb_controller()
515 writel(val, &usbctlr->utmip_hsrx_cfg0); in init_utmi_usb_controller()
518 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, in init_utmi_usb_controller()
526 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
528 if (controller->has_hostpc) { in init_utmi_usb_controller()
529 if (config->periph_id == PERIPH_ID_USBD) in init_utmi_usb_controller()
530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
532 if (config->periph_id == PERIPH_ID_USB2) in init_utmi_usb_controller()
533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
535 if (config->periph_id == PERIPH_ID_USB3) in init_utmi_usb_controller()
536 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
539 /* Finished the per-controller init. */ in init_utmi_usb_controller()
541 /* De-assert UTMIP_RESET to bring out of reset. */ in init_utmi_usb_controller()
542 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); in init_utmi_usb_controller()
545 for (loop_count = 100000; loop_count != 0; loop_count--) { in init_utmi_usb_controller()
546 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) in init_utmi_usb_controller()
551 return -ETIMEDOUT; in init_utmi_usb_controller()
554 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); in init_utmi_usb_controller()
560 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | in init_utmi_usb_controller()
562 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | in init_utmi_usb_controller()
565 if (controller->has_hostpc) { in init_utmi_usb_controller()
571 ((unsigned long)config->reg & USB1_ADDR_MASK); in init_utmi_usb_controller()
572 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); in init_utmi_usb_controller()
574 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
593 struct usb_ctlr *usbctlr = config->reg; in init_ulpi_usb_controller()
601 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { in init_ulpi_usb_controller()
603 * This GPIO is typically active-low, and marked as such in in init_ulpi_usb_controller()
608 * and the second call logically de-asserts the reset signal, in init_ulpi_usb_controller()
611 dm_gpio_set_value(&config->phy_reset_gpio, 1); in init_ulpi_usb_controller()
613 dm_gpio_set_value(&config->phy_reset_gpio, 0); in init_ulpi_usb_controller()
617 clock_enable(config->periph_id); in init_ulpi_usb_controller()
621 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, in init_ulpi_usb_controller()
628 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); in init_ulpi_usb_controller()
632 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
637 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
643 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
647 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; in init_ulpi_usb_controller()
659 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); in init_ulpi_usb_controller()
662 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); in init_ulpi_usb_controller()
663 for (loop_count = 100000; loop_count != 0; loop_count--) { in init_ulpi_usb_controller()
664 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) in init_ulpi_usb_controller()
669 return -ETIMEDOUT; in init_ulpi_usb_controller()
670 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); in init_ulpi_usb_controller()
680 return -ENOSYS; in init_ulpi_usb_controller()
699 config->reg = (struct usb_ctlr *)dev_read_addr(dev); in fdt_decode_usb()
700 debug("reg=%p\n", config->reg); in fdt_decode_usb()
704 config->dr_mode = DR_MODE_HOST; in fdt_decode_usb()
706 config->dr_mode = DR_MODE_DEVICE; in fdt_decode_usb()
708 config->dr_mode = DR_MODE_OTG; in fdt_decode_usb()
712 return -EINVAL; in fdt_decode_usb()
715 config->dr_mode = DR_MODE_HOST; in fdt_decode_usb()
719 config->utmi = phy && 0 == strcmp("utmi", phy); in fdt_decode_usb()
720 config->ulpi = phy && 0 == strcmp("ulpi", phy); in fdt_decode_usb()
721 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode"); in fdt_decode_usb()
722 config->periph_id = clock_decode_periph_id(dev); in fdt_decode_usb()
723 if (config->periph_id == PERIPH_ID_NONE) { in fdt_decode_usb()
725 return -EINVAL; in fdt_decode_usb()
727 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio, in fdt_decode_usb()
729 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0, in fdt_decode_usb()
730 &config->phy_reset_gpio, GPIOD_IS_OUT); in fdt_decode_usb()
732 config->has_legacy_mode, config->utmi, config->ulpi, in fdt_decode_usb()
733 config->periph_id, gpio_get_number(&config->vbus_gpio), in fdt_decode_usb()
734 gpio_get_number(&config->phy_reset_gpio), config->dr_mode, in fdt_decode_usb()
735 config->reg); in fdt_decode_usb()
746 switch (config->dr_mode) { in usb_common_init()
752 config->dr_mode); in usb_common_init()
753 return -1; in usb_common_init()
757 if (config->periph_id != PERIPH_ID_USBD) { in usb_common_init()
759 return -1; in usb_common_init()
761 if (!config->utmi) { in usb_common_init()
763 return -1; in usb_common_init()
765 switch (config->dr_mode) { in usb_common_init()
771 config->dr_mode); in usb_common_init()
772 return -1; in usb_common_init()
777 return -1; in usb_common_init()
780 debug("%d, %d\n", config->utmi, config->ulpi); in usb_common_init()
781 if (config->utmi) in usb_common_init()
783 else if (config->ulpi) in usb_common_init()
790 config->init_type = init; in usb_common_init()
799 usbctlr = priv->reg; in usb_common_uninit()
802 writel(0, &usbctlr->usb_cmd); in usb_common_uninit()
806 writel(2, &usbctlr->usb_cmd); in usb_common_uninit()
825 priv->type = dev_get_driver_data(dev); in ehci_usb_ofdata_to_platdata()
839 ret = usb_common_init(priv, plat->init_type); in ehci_usb_probe()
842 hccr = (struct ehci_hccr *)&priv->reg->cap_length; in ehci_usb_probe()
843 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; in ehci_usb_probe()
845 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); in ehci_usb_probe()
850 plat->init_type); in ehci_usb_probe()
854 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
855 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
856 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
857 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },